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1. 发明授权

US08719663B2 Cross-decoding for non-volatile storage 有权
标题翻译：用于非易失性存储的交叉解码
公开(公告)号：US08719663B2
公开(公告)日：2014-05-06
申请号：US13323769
申请日：2011-12-12
申请人： Yan Li , Hao Zhong
发明人： Yan Li , Hao Zhong
IPC分类号： G11C29/00
CPC分类号： G06F11/076 , G06F11/1072 , G06F12/0246 , G06F2212/7202 , H03M13/1102 , H03M13/2957
摘要： Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used.
摘要翻译：当对多级单元技术闪存的期望页进行解码时，交叉解码协助解码否则不可校正的错误。固态盘（SSD）控制器分别在各种页面（例如，上，中，下页）中调整分配给冗余的空间，使得各页具有相应的有效误码率（BER），可选地包括交叉解码，相互接近或者，控制器调整分配以均衡解码时间（或者可选地，访问时间），可选地包括当存在否则不可校正的错误时由于交叉解码而产生的解码时间（访问时间）。调整是通过（a）用于ECC冗余的分配和用户数据空间之间的相应比率，和/或（b）各种页面中的每一个的相应编码率和/或编码技术。或者，控制器通过分配冗余和各种页面的数据来调整分配以最大化总可用容量，假设要使用交叉解码。

2. 发明授权

US08245098B2 Selectively strengthening and weakening check-node messages in error-correction decoders 有权
标题翻译：在纠错解码器中选择性地加强和削弱校验节点消息
公开(公告)号：US08245098B2
公开(公告)日：2012-08-14
申请号：US12538915
申请日：2009-08-11
申请人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
发明人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.
摘要翻译：在一个实施例中，LDPC解码器具有多个校验节点单元（CNU）和控制器。最初，CNU基于由控制器选择的初始偏移值生成校验节点消息。如果解码器收敛于陷阱集合，则控制器为不满意的校验节点（MSC）（其位置近似）和/或不满足的校验节点（USC）选择新的偏移值。特别地，选择偏移值，使得（i）相对于MSC的消息相对于将使用初始偏移值生成的消息减少和/或（ii）相对于USC的消息相对于将使用初始偏移值生成的消息。然后继续解码指定数量的迭代以打破陷阱集。在其他实施例中，控制器选择缩放因子，而不是或附加于偏移值。

3. 发明授权

US07990642B2 Systems and methods for storage channel testing 有权
标题翻译：存储通道测试的系统和方法
公开(公告)号：US07990642B2
公开(公告)日：2011-08-02
申请号：US12425757
申请日：2009-04-17
申请人： Yuan Xing Lee , George Mathew , Shaohua Yang , Hongwei Song , Weijun Tan , Hao Zhong
发明人： Yuan Xing Lee , George Mathew , Shaohua Yang , Hongwei Song , Weijun Tan , Hao Zhong
IPC分类号： G11B27/36
CPC分类号： G11B20/182 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.
摘要翻译：本发明的各种实施例提供用于验证存储设备的元件的系统和方法。作为示例，本发明的各种实施例提供包括写入路径电路，读取路径电路和验证电路的半导体器件。写入路径电路可操作用于接收数据输入并将数据输入转换成适合于存储的写数据到存储介质。读路径电路可操作以接收读数据并将读数据转换为数据输出。验证电路可操作以：接收写入数据，用第一噪声序列增加写入数据以产生第一增强数据序列; 并且用第二噪声序列来增加第一增强数据序列的导数以产生读取的数据。

4. 发明申请

US20110029826A1 Systems and Methods for Re-using Decoding Parity in a Detector Circuit 有权
标题翻译：在检测器电路中重新使用解码奇偶校验的系统和方法
公开(公告)号：US20110029826A1
公开(公告)日：2011-02-03
申请号：US12510859
申请日：2009-07-28
申请人： Hao Zhong , Weijun Tan , Yang Han , Zongwang Li , Shaohua Yang , Yuan Xing Lee
发明人： Hao Zhong , Weijun Tan , Yang Han , Zongwang Li , Shaohua Yang , Yuan Xing Lee
IPC分类号： H03M13/41 , H03M13/13 , G06F11/10
CPC分类号： H03M13/1157 , H03M13/1102 , H03M13/114 , H03M13/2957 , H03M13/2975 , H03M13/3746 , H03M13/3994 , H03M13/41 , H03M13/6331
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving an LDPC codeword, and grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit. The series of data bits satisfies an LDPC parity equation.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种用于数据处理的方法，其包括接收LDPC码字，以及将来自LDPC码字的活动比特分组为包括一个或多个用户数据比特和至少一个LDPC奇偶校验位的一系列数据比特。一系列数据位满足LDPC奇偶校验方程。

5. 发明申请

US20100100788A1 Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
标题翻译：用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器
公开(公告)号：US20100100788A1
公开(公告)日：2010-04-22
申请号：US12288221
申请日：2008-10-17
申请人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
发明人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
IPC分类号： H03M13/27 , G06F11/10
CPC分类号： H03M13/05 , G06F11/1008 , H03M13/116 , H03M13/2792
摘要： The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
摘要翻译：本发明是用于编码用户数据的可编程QC LDPC编码器。编码器可以被配置为用读通道实现。编码器可以包括多个桶形移位器电路。桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。桶形移位器电路还被配置为输出奇偶校验位。编码器还可以包括编码器交织器存储器。编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。编码器交织器可以被配置为交织奇偶校验位。此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

6. 发明申请

US20090273492A1 Systems and Methods for Queue Based Data Detection and Decoding 有权
标题翻译：基于队列数据检测和解码的系统和方法
公开(公告)号：US20090273492A1
公开(公告)日：2009-11-05
申请号：US12114462
申请日：2008-05-02
申请人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
发明人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： H03M7/00
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括至少第一检测器，第二检测器，解码器和排队缓冲器的可变迭代数据处理系统。第一检测器可操作以在第一时间对输入数据集执行数据检测。解码器接收来自第一检测器的输出的导出并执行解码处理。在解码过程不能收敛的情况下，解码器输出被传送到第二检测器用于随后的检测和解码过程。

7. 发明申请

US20090268575A1 Systems and Methods for Reducing Attenuation of Information Derived from a Defective Medium 有权
标题翻译：减少缺陷介质信息衰减的系统和方法
公开(公告)号：US20090268575A1
公开(公告)日：2009-10-29
申请号：US12111889
申请日：2008-04-29
申请人： Weijun Tan , Hao Zhong , Yuan Xing Lee , Richard Rauschmayer , Shaohua Yang , Harley Burger , Kelly Fitzpatrick , Changyou Xu
发明人： Weijun Tan , Hao Zhong , Yuan Xing Lee , Richard Rauschmayer , Shaohua Yang , Harley Burger , Kelly Fitzpatrick , Changyou Xu
IPC分类号： G11B20/18
CPC分类号： G11B20/18 , G11B20/10009 , G11B20/10287 , G11B20/10296 , H03M13/3905 , H03M13/3961 , H03M13/4146 , H03M13/6343 , H03M13/658
摘要： Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.
摘要翻译：本发明的各种实施例提供了用于数据再生的系统和方法。例如，公开了一种用于数据再生的方法，包括接收从介质导出的数据输入，确定与数据输入相对应的介质缺陷，以及确定与缺陷介质相关联的衰减因子。至少部分地基于介质有缺陷的确定，通过衰减因子的导数来放大输入的数据以再生数据。

8. 发明授权

US09329948B2 Measuring cell damage for wear leveling in a non-volatile memory 有权
标题翻译：在非易失性存储器中测量电容器损坏
公开(公告)号：US09329948B2
公开(公告)日：2016-05-03
申请号：US13620982
申请日：2012-09-15
申请人： Yan Li , Alexander Hubris , Hao Zhong
发明人： Yan Li , Alexander Hubris , Hao Zhong
IPC分类号： G11C29/00 , G06F11/16 , G06F12/02 , G11C16/34 , G11C29/42 , G11C29/50 , G11C29/52
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7211 , G11C16/3495 , G11C29/42 , G11C29/50 , G11C29/52
摘要： An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.
摘要翻译： NVM控制器测量NVM中磨损均衡的单元损坏，从而提高存储子系统（如SSD）的性能，可靠性，寿命和/或成本。在第一方面，控制器确定读取NVM的页面的错误是由于单元损坏和/或单元泄漏引起的。控制器重新编程并立即读回页面，如果在立即读取期间检测到错误，则检测到错误是由单元损坏引起的。在第二方面，通过更新针对NVM的页面和/或块的单元损坏计数器跟踪单元损坏。在第三方面，至少部分地基于对NVM的页面和/或块的所测量的单元损坏来执行损耗均衡。

9. 发明申请

US20140082459A1 MEASURING CELL DAMAGE FOR WEAR LEVELING IN A NON-VOLATILE MEMORY 有权
标题翻译：测量非易失性存储器中的磨损细胞损伤
公开(公告)号：US20140082459A1
公开(公告)日：2014-03-20
申请号：US13620982
申请日：2012-09-15
申请人： Yan LI , Alexander HUBRIS , Hao ZHONG
发明人： Yan LI , Alexander HUBRIS , Hao ZHONG
IPC分类号： G06F11/16
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7211 , G11C16/3495 , G11C29/42 , G11C29/50 , G11C29/52
摘要： An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.
摘要翻译： NVM控制器测量NVM中磨损均衡的单元损坏，从而提高存储子系统（如SSD）的性能，可靠性，寿命和/或成本。在第一方面，控制器确定读取NVM的页面的错误是由于单元损坏和/或单元泄漏引起的。控制器重新编程并立即读回页面，如果在立即读取期间检测到错误，则检测到错误是由单元损坏引起的。在第二方面，通过更新针对NVM的页面和/或块的单元损坏计数器跟踪单元损坏。在第三方面，至少部分地基于对NVM的页面和/或块的所测量的单元损坏来执行损耗均衡。

10. 发明申请

US20120284585A1 Systems and Methods for Queue Based Data Detection and Decoding 有权
标题翻译：基于队列数据检测和解码的系统和方法
公开(公告)号：US20120284585A1
公开(公告)日：2012-11-08
申请号：US13547940
申请日：2012-07-12
申请人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
发明人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for variable iteration data processing.
摘要翻译：本发明的各种实施例提供了用于可变迭代数据处理的系统和方法。

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