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1. 发明申请

US20130148733A1 MOTION ESTIMATION APPARATUS AND METHOD 审中-公开
标题翻译：运动估计装置和方法
公开(公告)号：US20130148733A1
公开(公告)日：2013-06-13
申请号：US13556497
申请日：2012-07-24
申请人： Seong Mo PARK , Nak Woong Eum , Hee-Bum Jung
发明人： Seong Mo PARK , Nak Woong Eum , Hee-Bum Jung
IPC分类号： H04N7/32
CPC分类号： H04N19/426 , H04N19/51 , H04N19/57
摘要： Disclosed are motion estimation apparatus and method. The present invention can reduce an external memory access in an area in which a macroblock is large while preventing image quality from deteriorating due to motion estimation according to coding units, by obtaining a minimum motion vector using a prediction method in 64×64 and 32×32 modes for the coding units meeting a high efficiency video coding (HEVC) standard and obtaining a motion vector using a full search method in other modes.
摘要翻译：公开了运动估计装置和方法。本发明可以通过使用64×64和32×64的预测方法获得最小运动矢量来减少宏块大的区域中的外部存储器访问，同时通过根据编码单位的运动估计来防止图像质量劣化满足高效率视频编码（HEVC）标准的编码单元的32种模式，并且在其他模式中使用全搜索方法获得运动矢量。

2. 发明申请

US20120143602A1 SPEECH DECODER AND METHOD FOR DECODING SEGMENTED SPEECH FRAMES 审中-公开
标题翻译：语音解码器和解码分离的语音框架的方法
公开(公告)号：US20120143602A1
公开(公告)日：2012-06-07
申请号：US13191007
申请日：2011-07-26
申请人： Kyung Jin BYUN , Nak Woong EUM , Hee-Bum JUNG
发明人： Kyung Jin BYUN , Nak Woong EUM , Hee-Bum JUNG
IPC分类号： G10L19/00
CPC分类号： G10L19/06 , G10L19/005
摘要： A method for decoding segmented speech frames includes: generating parameters of a segmented current speech frame by using parameters of a segmented previous speech frame; and decoding a speech frame by using the parameters of the current speech frame, which are generated in the generating of the parameters of the segmented current speech frame.
摘要翻译：解码分段语音帧的方法包括：通过使用分段的先前语音帧的参数来产生分段的当前语音帧的参数; 以及通过使用在分割的当前语音帧的参数的生成中生成的当前语音帧的参数来解码语音帧。

3. 发明授权

US07899667B2 Waveform interpolation speech coding apparatus and method for reducing complexity thereof 有权
标题翻译：用于降低其复杂度的波形插值语音编码装置和方法
公开(公告)号：US07899667B2
公开(公告)日：2011-03-01
申请号：US11641226
申请日：2006-12-19
申请人： Kyung-Jin Byun , Ik-Soo Eo , Hee-Bum Jung , Nak-Woong Eum
发明人： Kyung-Jin Byun , Ik-Soo Eo , Hee-Bum Jung , Nak-Woong Eum
IPC分类号： G10L19/14
CPC分类号： G10L19/097
摘要： A waveform interpolation speech coding apparatus and method for reducing complexity thereof are disclosed. The waveform interpolation speech coding apparatus includes: a waveform interpolation encoding unit for receiving a speech signal, calculating parameters for a waveform interpolation from the received speech signal, and quantizing the calculating parameters; and a realignment parameter calculating unit for restoring a characteristic waveform (CW) using the quantized parameter, calculating a realignment parameter that maximizes a cross-correlation among consecutive CWs for the restored CW.
摘要翻译：公开了一种用于降低其复杂度的波形插值语音编码装置和方法。波形插值语音编码装置包括：波形内插编码单元，用于接收语音信号，从接收的语音信号计算波形内插的参数，并量化所述计算参数; 以及重新对准参数计算单元，用于使用量化参数恢复特征波形（CW），计算使恢复的CW中连续CW之间的互相关最大化的重新对准参数。

4. 发明授权

US07464275B2 Apparatus for sequentially enabling and disabling multiple powers 失效
标题翻译：用于顺序启用和禁用多个功率的装置
公开(公告)号：US07464275B2
公开(公告)日：2008-12-09
申请号：US11213059
申请日：2005-08-26
申请人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
发明人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.
摘要翻译：本发明提供了一种用于控制多个功率的装置，其能够在要提供给诸如液晶显示器（LCD）模块的多个功率的系统或组件的优先级中打开和关闭多个功率。在用于控制多个功率的装置中，将高电平的接通信号施加到输入端，并且每当时钟被施加到时钟信号输入端时，控制信号产生单元的输出被顺序地改变为高电平一个周期，从而顺序输出多个功率的输出。此外，只要将时钟施加到时钟信号输入端子一个周期，则将低电平的关闭信号施加到输入端子，并且控制信号产生单元的输出以反转次序改变为低电平，使得多个功率的输出以反转顺序中断。

5. 发明授权

US07391632B2 Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same 失效
标题翻译：选择性地执行快速hasamard变换和快速傅里叶变换的装置，以及使用其的CCK调制和解调装置
公开(公告)号：US07391632B2
公开(公告)日：2008-06-24
申请号：US11273727
申请日：2005-11-14
申请人： Tae-Joon Kim , Ik-Soo Eo , Kyung-Soo Kim , Hee-Bum Jung
发明人： Tae-Joon Kim , Ik-Soo Eo , Kyung-Soo Kim , Hee-Bum Jung
IPC分类号： G11C19/08
CPC分类号： G06F17/142 , G06F17/145
摘要： A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.
摘要翻译：用于选择性地执行快速Hadamard变换（FHT）的快速傅里叶变换（FFT）装置和使用该快速傅立叶变换的补码代码键控（CCK）调制/解调装置。通过在OFDM模块中实现使用FFT结构的CCK调制，将OFDM模块和CCK模块集成为具有比传统方案更低复杂度的模块，并且在OFDM模块中体现了使用FFT结构的次优和优化的CCK调制。 CDMA，OFDM，CCK模块可以集成为单个模块。

6. 发明申请

US20080012745A1 APPARATUS FOR GENERATING RANGING BINARY CODE SEQUENCE AT HIGH-SPEED, AND METHOD THEREOF 失效
标题翻译：用于生成高速度的二进制代码序列的装置及其方法
公开(公告)号：US20080012745A1
公开(公告)日：2008-01-17
申请号：US11689547
申请日：2007-03-22
申请人： YoungSeok BAEK , Jung-Bum KIM , Kyung-Soo KIM , Iksoo EO , Hee-Bum JUNG
发明人： YoungSeok BAEK , Jung-Bum KIM , Kyung-Soo KIM , Iksoo EO , Hee-Bum JUNG
IPC分类号： H04L17/02
CPC分类号： G01S1/68 , H04W64/00
摘要： Provided is an apparatus for generating a ranging binary code sequence at a high-speed, and a method thereof. The apparatus includes: an initial register value generator for generating initial register values of minimum valid ranging codes; a storage for storing the generated initial register values of the valid ranging codes(≦K, where K is the ranging value transmitted by base station); a binary code sequence generator for generating a binary code sequence of a corresponding ranging code; and a procedure for incrementally updating the initial register values as receiving the new ranging code from base station.
摘要翻译：提供了一种用于高速生成测距二进制码序列的装置及其方法。该装置包括：初始寄存器值发生器，用于产生最小有效测距码的初始寄存器值; 用于存储生成的有效测距码的初始寄存器值的存储器（<= K，其中K是由基站发送的测距值）; 用于产生相应测距码的二进制码序列的二进制码序列发生器; 以及用于在从基站接收新的测距码时逐渐更新初始寄存器值的过程。

7. 发明申请

US20070237246A1 Wireless modem, modulator, and demodulator 审中-公开
标题翻译：无线调制解调器，调制器和解调器
公开(公告)号：US20070237246A1
公开(公告)日：2007-10-11
申请号：US11496897
申请日：2006-08-01
申请人： In Gi Lim , Hyung Il Park , Young Seok Baek , Hyuk Kim , Tae Joon Kim , Kyung Soo Kim , Ik Soo Eo , Hee Bum Jung
发明人： In Gi Lim , Hyung Il Park , Young Seok Baek , Hyuk Kim , Tae Joon Kim , Kyung Soo Kim , Ik Soo Eo , Hee Bum Jung
IPC分类号： H04K1/10
CPC分类号： H04L27/2662 , H04L1/0041 , H04L1/0045 , H04L1/0071 , H04L5/06 , H04L27/2657
摘要： A wireless modem is mounted to a terminal for wireless communication, and specifically controls an internal drive clock to reduce power consumption in an active mode. The wireless modem includes: a wireless core module for transmitting and receiving a radio signal; a modulator for converting data to be transmitted into a wireless transmission signal and transmitting the converted signal to the wireless core module; a demodulator for converting the signal received from the wireless core module into reception data; a synchronizer for synchronizing the signal received from the wireless core module; and a clock controller for generating a drive clock of each of the modulator, the demodulator, and the synchronizer. A low power clock controller is divided into six main functional blocks of a synchronizer, an analog controller, a modulator, a channel decoder, a demodulator, and a channel encoder, and has a feature that a clock is input only when a main functional block operates. As a result, it is possible to minimize power consumption caused by clock switching when an Orthogonal Frequency Division Multiplexing Access (OFDMA) mobile station modem operates in an active mode through the clock controller.
摘要翻译：无线调制解调器被安装到用于无线通信的终端，并且具体地控制内部驱动时钟以降低活动模式中的功耗。无线调制解调器包括：用于发送和接收无线电信号的无线核心模块; 用于将要发送的数据转换成无线发送信号并将转换的信号发送到无线核心模块的调制器; 解调器，用于将从无线核心模块接收的信号转换为接收数据; 用于使从所述无线核心模块接收的信号同步的同步器; 以及时钟控制器，用于产生调制器，解调器和同步器中的每一个的驱动时钟。低功率时钟控制器被分为同步器，模拟控制器，调制器，信道解码器，解调器和信道编码器的六个主要功能块，并且具有仅当主功能块操作。结果，当正交频分复用接入（OFDMA）移动台调制解调器通过时钟控制器以活动模式操作时，可以最小化由时钟切换引起的功率消耗。

8. 发明申请

US20070133700A1 Method for blind channel estimation 有权
标题翻译：盲信道估计方法
公开(公告)号：US20070133700A1
公开(公告)日：2007-06-14
申请号：US11634276
申请日：2006-12-05
申请人： Tae Joon Kim , Ik Soo Eo , Hee Bum Jung
发明人： Tae Joon Kim , Ik Soo Eo , Hee Bum Jung
IPC分类号： H04K1/10 , H04B1/10
CPC分类号： H04L25/0238 , H04L25/0212 , H04L25/0248
摘要： Provided is a method for channel estimation increasing frequency band efficiency lost by using a pilot, and reducing sensitivity to channel zero, instability, and complexity. The method includes the steps of: (a) generating an i-th symbol block Si including N carriers; (b) performing an inverse fast Fourier transform (IFFT) operation on the i-th symbol block and forming an orthogonal frequency division multiplexing (OFDM) symbol block; (c) attaching a guard interval sample in front of the i-th OFDM symbol block Ui and forming at least one OFDM symbol block Ui,cp; and (d) modeling the formed OFDM symbol block Ui,cp with a channel finite impulse response (FIR) filter h and noise v and estimating channel impulse response using signals yi received through a channel.
摘要翻译：提供了一种用于信道估计的方法，其通过使用导频来增加频带效率损失，并降低对信道零的灵敏度，不稳定性和复杂性。该方法包括以下步骤：（a）产生包括N个载波的第i个符号块S i i; （b）对第i个符号块执行快速傅里叶逆变换（IFFT），形成正交频分复用（OFDM）符号块; （c）在第i个OFDM符号块U 1 i前面附加保护间隔样本，并形成至少一个OFDM符号块U i，c p; 以及（d）利用信道有限脉冲响应（FIR）滤波器h和噪声v对所形成的OFDM符号块U i，c p进行建模，并使用通过信道接收的信号y i来估计信道脉冲响应。

9. 发明授权

US06833766B2 Adaptive loop gain control circuit for voltage controlled oscillator 失效
标题翻译：用于压控振荡器的自适应环路增益控制电路
公开(公告)号：US06833766B2
公开(公告)日：2004-12-21
申请号：US10410829
申请日：2003-04-09
申请人： Kwi-dong Kim , Jong-kee Kwon , Hee-bum Jung , Kyung-soo Kim
发明人： Kwi-dong Kim , Jong-kee Kwon , Hee-bum Jung , Kyung-soo Kim
IPC分类号： H03L700
CPC分类号： H03L1/00 , H03L7/0995
摘要： There is provided an adaptive loop gain control circuit for a voltage-controlled oscillator (VCO). The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) includes a detected voltage generating unit which generates a detected voltage signal according to changes in an operating voltage and an operating temperature, and a control circuit unit which outputs an oscillation control current signal according to the detected voltage signal and an input control voltage signal. The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) compensates for an oscillation control current according to changes in operating voltage and temperature and compensates for the gain of a phase locked loop (PLL) system, thereby ensuring high operating stability in the PLL circuit.
摘要翻译：提供了一种用于压控振荡器（VCO）的自适应环路增益控制电路。用于压控振荡器（VCO）的自适应环路增益控制电路包括：检测电压产生单元，其根据工作电压和工作温度的变化产生检测的电压信号;以及控制电路单元，其输出振荡控制电流信号根据检测到的电压信号和输入控制电压信号。用于压控振荡器（VCO）的自适应环路增益控制电路根据工作电压和温度的变化补偿振荡控制电流，并补偿锁相环（PLL）系统的增益，从而确保在 PLL电路。

10. 发明授权

US06400932B1 Low offset automatic frequency tuning circuits for continuous-time filter 有权
标题翻译：低偏移自动频率调谐电路，用于连续时间滤波
公开(公告)号：US06400932B1
公开(公告)日：2002-06-04
申请号：US09454389
申请日：1999-12-03
申请人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
发明人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
IPC分类号： H04B118
CPC分类号： H03H11/0422 , H03L7/06
摘要： The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.
摘要翻译：调谐电路技术领域本发明涉及一种调谐电路，更具体地说涉及一种用于连续时间滤波器的调谐电路，其能够精确地确定Gm值，以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化，时间过滤器。根据本发明，提供了一种频率调谐电路，其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置，用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样，并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置，用于通过将从外部输入的时钟分频，将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号，从积分装置获取值，并比较这些信号的实际交点和目标交点; 以及控制装置，用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差，产生控制信号以调节积分装置和偏移采样装置的Gm值。

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