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1. 发明授权

US07464275B2 Apparatus for sequentially enabling and disabling multiple powers 失效
标题翻译：用于顺序启用和禁用多个功率的装置
公开(公告)号：US07464275B2
公开(公告)日：2008-12-09
申请号：US11213059
申请日：2005-08-26
申请人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
发明人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.
摘要翻译：本发明提供了一种用于控制多个功率的装置，其能够在要提供给诸如液晶显示器（LCD）模块的多个功率的系统或组件的优先级中打开和关闭多个功率。在用于控制多个功率的装置中，将高电平的接通信号施加到输入端，并且每当时钟被施加到时钟信号输入端时，控制信号产生单元的输出被顺序地改变为高电平一个周期，从而顺序输出多个功率的输出。此外，只要将时钟施加到时钟信号输入端子一个周期，则将低电平的关闭信号施加到输入端子，并且控制信号产生单元的输出以反转次序改变为低电平，使得多个功率的输出以反转顺序中断。

2. 发明授权

US06400932B1 Low offset automatic frequency tuning circuits for continuous-time filter 有权
标题翻译：低偏移自动频率调谐电路，用于连续时间滤波
公开(公告)号：US06400932B1
公开(公告)日：2002-06-04
申请号：US09454389
申请日：1999-12-03
申请人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
发明人： Chang Jun Oh , Jong Kee Kwon , Jong Ryul Lee , Won Chul Song , Hee Bum Jung , Kyung Soo Kim , Han Jin Cho , Ook Kim
IPC分类号： H04B118
CPC分类号： H03H11/0422 , H03L7/06
摘要： The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.
摘要翻译：调谐电路技术领域本发明涉及一种调谐电路，更具体地说涉及一种用于连续时间滤波器的调谐电路，其能够精确地确定Gm值，以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化，时间过滤器。根据本发明，提供了一种频率调谐电路，其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置，用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样，并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置，用于通过将从外部输入的时钟分频，将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号，从积分装置获取值，并比较这些信号的实际交点和目标交点; 以及控制装置，用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差，产生控制信号以调节积分装置和偏移采样装置的Gm值。

3. 发明授权

US08188801B2 Delay circuit for low power ring oscillator 失效
标题翻译：低功耗环形振荡器的延迟电路
公开(公告)号：US08188801B2
公开(公告)日：2012-05-29
申请号：US12878476
申请日：2010-09-09
申请人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
发明人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/012
摘要： Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.
摘要翻译：这里公开了一种用于低功率环形振荡器的延迟电路。延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

4. 发明授权

US07830959B2 Apparatus and method for performing intra prediction for image decoder 有权
标题翻译：用于对图像解码器进行帧内预测的装置和方法
公开(公告)号：US07830959B2
公开(公告)日：2010-11-09
申请号：US10876739
申请日：2004-06-28
申请人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
发明人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/436 , H04N19/105 , H04N19/186 , H04N19/423 , H04N19/44 , H04N19/593
摘要： Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16×16 luminance component and 4×4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.
摘要翻译：提供了一种用于对图像解码器进行帧内预测的装置和方法，其中通过使用与从外部设备输入的图像数据相邻的水平/垂直块，相对于16×16亮度分量并行执行帧内预测，图像数据的4×4亮度分量，然后相对于色度分量，从而最大化系统的效率，不仅减少了执行时间和硬件成本，而且提高了处理速度。

5. 发明申请

US20100150041A1 WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
标题翻译：具有自我感应功能的无线通信设备
公开(公告)号：US20100150041A1
公开(公告)日：2010-06-17
申请号：US12430313
申请日：2009-04-27
申请人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
发明人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
IPC分类号： G08C17/00
CPC分类号： H04Q9/02 , H04Q2209/43 , H04Q2209/883
摘要： Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.
摘要翻译：公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

6. 发明授权

US07554355B2 Crossbar switch architecture for multi-processor SoC platform 有权
标题翻译：交叉开关架构为多处理器SoC平台
公开(公告)号：US07554355B2
公开(公告)日：2009-06-30
申请号：US11607515
申请日：2006-12-01
申请人： June Young Chang , Han Jin Cho
发明人： June Young Chang , Han Jin Cho
IPC分类号： H04L12/50 , H03K17/00
CPC分类号： H04L49/101 , H04L49/15 , H04L49/45
摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
摘要翻译：提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易增加并具有简单的控制结构。交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与每行最后一列的多路复用器与该行的输入/输出线连接。

7. 发明授权

US08630217B2 Wireless communications terminal having RF direct wakeup function and wakeup method thereof 有权
标题翻译：具有RF直接唤醒功能的无线通信终端及其唤醒方法
公开(公告)号：US08630217B2
公开(公告)日：2014-01-14
申请号：US13342676
申请日：2012-01-03
申请人： Han Jin Cho , Jae Hyung Lee , Myeung Su Kim , Joon Hyung Lim , Tah Joon Park
发明人： Han Jin Cho , Jae Hyung Lee , Myeung Su Kim , Joon Hyung Lim , Tah Joon Park
IPC分类号： H04W52/02
CPC分类号： H04W52/0235 , Y02D70/166
摘要： A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.
摘要翻译：无线通信终端包括：RF唤醒检测单元，检测包括用于唤醒的RF ID的第一RF信号; 以及当由所述RF唤醒检测单元检测到的所述第一RF信号中包含的RF ID与睡眠模式中的预设参考ID匹配时，所述无线通信单元被唤醒。

8. 发明申请

US20090147841A1 DISTRIBUTED VIDEO CODING APPARATUS AND METHOD CAPABLE OF CONTROLLING ENCODING RATE 失效
标题翻译：分布式视频编码设备和能够控制编码速率的方法
公开(公告)号：US20090147841A1
公开(公告)日：2009-06-11
申请号：US12142708
申请日：2008-06-19
申请人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

9. 发明申请

US20070126474A1 Crossbar switch architecture for multi-processor SoC platform 有权
标题翻译：交叉开关架构为多处理器SoC平台
公开(公告)号：US20070126474A1
公开(公告)日：2007-06-07
申请号：US11607515
申请日：2006-12-01
申请人： June Young Chang , Han Jin Cho
发明人： June Young Chang , Han Jin Cho
IPC分类号： H03K19/173
CPC分类号： H04L49/101 , H04L49/15 , H04L49/45
摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
摘要翻译：提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易增加并具有简单的控制结构。交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与每行最后一列的多路复用器与该行的输入/输出线连接。

10. 发明授权

US07020832B2 Turbo decoder and its calculation methods having a state metric 失效
公开(公告)号：US07020832B2
公开(公告)日：2006-03-28
申请号：US10039005
申请日：2001-12-31
申请人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
发明人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
IPC分类号： H03M13/03
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/6502 , H03M13/6505
摘要： The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

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