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1. 发明授权

US09548206B2 Ohmic contact structure for group III nitride semiconductor device having improved surface morphology and well-defined edge features 有权
标题翻译：具有改进的表面形态和良好限定的边缘特征的III族氮化物半导体器件的欧姆接触结构
公开(公告)号：US09548206B2
公开(公告)日：2017-01-17
申请号：US13182679
申请日：2011-07-14
申请人： Helmut Hagleitner , Jason Gurganus
发明人： Helmut Hagleitner , Jason Gurganus
IPC分类号： H01L29/45 , H01L21/285 , H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L29/452 , H01L21/28575 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.
摘要翻译：公开了用于III族氮化物半导体器件的欧姆接触结构的实施例及其制造方法。通常，欧姆接触结构的均方根（RMS）表面粗糙度小于10纳米，更优选小于或等于7.5纳米，更优选小于或等于5纳米，更优选地小于或等于2纳米，甚至更优选小于或等于1.5纳米。

2. 发明授权

US08907350B2 Semiconductor devices having improved adhesion and methods of fabricating the same 有权
标题翻译：具有改进的附着力的半导体器件及其制造方法
公开(公告)号：US08907350B2
公开(公告)日：2014-12-09
申请号：US12769307
申请日：2010-04-28
申请人： Van Mieczkowski , Helmut Hagleitner
发明人： Van Mieczkowski , Helmut Hagleitner
IPC分类号： H01L29/15 , H01L29/778 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/0649 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed.
摘要翻译：宽带隙半导体器件通过提供宽带隙半导体层制造，在宽带隙半导体层中提供多个凹槽，并在多个凹槽中提供金属栅极接触。可以在宽带隙半导体层上设置保护层，保护层具有延伸穿过其的第一开口，电介质层可以设置在保护层上，电介质层具有延伸穿过的第二开口，该第二开口窄于第一开口并且可以在第一和第二开口中设置栅极接触。可以提供金属栅极接触以在多个凹部中包括阻挡金属层，以及在远离宽带隙半导体层的阻挡金属层上的电流扩散层。还讨论了相关设备和制造方法。

3. 发明授权

US08896122B2 Semiconductor devices having gates including oxidized nickel 有权
标题翻译：具有包括氧化镍的栅极的半导体器件
公开(公告)号：US08896122B2
公开(公告)日：2014-11-25
申请号：US12778334
申请日：2010-05-12
申请人： Van Mieczkowski , Helmut Hagleitner , Kevin Haberern
发明人： Van Mieczkowski , Helmut Hagleitner , Kevin Haberern
IPC分类号： H01L21/335 , H01L29/778 , H01L29/24 , H01L29/80 , H01L29/66 , H01L29/47 , H01L29/812 , H01L29/872 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/66871 , H01L29/7786 , H01L29/812 , H01L29/872
摘要： Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.
摘要翻译：提供肖特基势垒半导体器件，其包括宽带隙半导体层和宽带隙半导体层上的栅极。栅极包括在包括氧化镍（NiO）层的宽带隙半导体层上的金属层。本文还提供了相关制造装置的方法。

4. 发明授权

US08202796B2 Method of forming vias in silicon carbide and resulting devices and circuits 有权
标题翻译：在碳化硅和所产生的器件和电路中形成通孔的方法
公开(公告)号：US08202796B2
公开(公告)日：2012-06-19
申请号：US13021833
申请日：2011-02-07
申请人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
发明人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
IPC分类号： H01L21/28
CPC分类号： H01L29/452 , H01L21/30604 , H01L21/3081 , H01L21/445 , H01L21/76898 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/7787 , H01L29/812
摘要： A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.
摘要翻译：公开了一种在碳化硅衬底上制造集成电路的方法，其消除引线接合。该方法包括在硅碳化物衬底的表面上制造外延层中的半导体器件，并且在外延层的最上表面上具有用于器件的至少一个金属接触。然后将基板的相对表面研磨抛光直到基本透明。然后对碳化硅衬底的抛光表面进行掩模，以限定与设备金属接触相对的至少一个通孔的预定位置，并在步骤中蚀刻所需的通孔。第一蚀刻步骤在期望的掩蔽位置上蚀刻通过碳化硅衬底，直到蚀刻到达外延层。第二蚀刻步骤通过外延层蚀刻到器件触点。最后，通孔被金属化。

5. 发明授权

US08138583B2 Diode having reduced on-resistance and associated method of manufacture 有权
标题翻译：二极管具有降低的导通电阻和相关的制造方法
公开(公告)号：US08138583B2
公开(公告)日：2012-03-20
申请号：US11675658
申请日：2007-02-16
申请人： Saptharishi Sriram , Thomas J. Smith, Jr. , Helmut Hagleitner
发明人： Saptharishi Sriram , Thomas J. Smith, Jr. , Helmut Hagleitner
IPC分类号： H01L29/15
CPC分类号： H01L29/1608 , H01L23/291 , H01L23/31 , H01L29/0657 , H01L29/6606 , H01L29/6609 , H01L29/861 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.
摘要翻译：在正向偏置状态下具有降低的导通电阻的二极管结构包括优选为碳化硅的半导体层。器件的阳极和阴极位于底部半导体层的同一侧，提供横跨二极管体的横向导通。阳极定位在半导体台面上，并且台面的侧面被从阳极延伸到底层的非导电间隔物覆盖。欧姆接触，优选金属硅化物，覆盖在间隔物材料和阴极之间的底层的表面。导电路径从阳极延伸穿过台面的主体并穿过底部半导体层，包括欧姆接触。形成二极管的方法包括在二极管的适当区域上反应硅和金属层以形成金属硅化物的欧姆接触。

6. 发明授权

US07892974B2 Method of forming vias in silicon carbide and resulting devices and circuits 有权
标题翻译：在碳化硅和所产生的器件和电路中形成通孔的方法
公开(公告)号：US07892974B2
公开(公告)日：2011-02-22
申请号：US11551286
申请日：2006-10-20
申请人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
发明人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
IPC分类号： H01L21/44
CPC分类号： H01L29/452 , H01L21/30604 , H01L21/3081 , H01L21/445 , H01L21/76898 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/7787 , H01L29/812
摘要： A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, metallizing the via provides an electrical path from the first surface of the substrate to the metal contact and to the device on the second surface of the substrate.
摘要翻译：公开了一种在碳化硅衬底上制造集成电路的方法，其消除了否则会导致不期望的电感的引线接合。该方法包括在硅碳化物衬底的表面上制造外延层中的半导体器件，并且在外延层的最上表面上具有用于器件的至少一个金属接触。然后将基板的相对表面研磨抛光直到基本透明。该方法然后包括掩盖碳化硅衬底的抛光表面，以限定用于至少一个通孔的预定位置，其与外延层的最上表面上的器件金属接触相对，并在步骤中蚀刻所需的通孔。第一蚀刻步骤在期望的掩蔽位置上蚀刻通过碳化硅衬底，直到蚀刻到达外延层。第二蚀刻步骤通过外延层蚀刻到器件触点。最后，通孔的金属化提供了从衬底的第一表面到金属接触件和衬底的第二表面上的器件的电路径。

7. 发明授权

US07525122B2 Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides 有权
标题翻译：使用无氢溅射氮化物钝化宽带隙基半导体器件
公开(公告)号：US07525122B2
公开(公告)日：2009-04-28
申请号：US11169378
申请日：2005-06-29
申请人： Zoltan Ring , Helmut Hagleitner , Jason Patrick Henning , Andrew Mackenzie , Scott Allen , Scott Thomas Sheppard , Richard Peter Smith , Saptharishi Sriram , Allan Ward, III
发明人： Zoltan Ring , Helmut Hagleitner , Jason Patrick Henning , Andrew Mackenzie , Scott Allen , Scott Thomas Sheppard , Richard Peter Smith , Saptharishi Sriram , Allan Ward, III
IPC分类号： H01L29/15 , H01L31/0256
CPC分类号： H01L21/045 , H01L21/3145 , H01L21/318 , H01L21/3185 , H01L29/1608 , H01L29/2003 , H01L29/24
摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.
摘要翻译：公开了钝化的半导体结构和相关方法。该结构包括碳化硅衬底或层; 在碳化硅衬底上的氧化层，用于降低碳化硅衬底和热氧化层之间的界面密度; 在热氧化层上的第一溅射的非化学计量的氮化硅层，用于减少寄生电容并最小化器件捕获; 在所述第一层上的第二溅射的非化学计量的氮化硅层，用于使所述衬底进一步从所述衬底定位以后的钝化层而不封装所述结构; 在第二溅射层上溅射化学计量的氮化硅层，用于封装该结构并增强钝化层的氢阻挡性能; 以及化学气相沉积的化学计量氮化硅的环境阻挡层，用于在封装层上进行步骤覆盖和防裂。

8. 发明申请

US20090104738A1 Method of Forming Vias in Silicon Carbide and Resulting Devices and Circuits 有权
标题翻译：在碳化硅和所得装置和电路中形成通孔的方法
公开(公告)号：US20090104738A1
公开(公告)日：2009-04-23
申请号：US11551286
申请日：2006-10-20
申请人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
发明人： Zoltan Ring , Scott Thomas Sheppard , Helmut Hagleitner
IPC分类号： H01L21/335 , H01L21/768
CPC分类号： H01L29/452 , H01L21/30604 , H01L21/3081 , H01L21/445 , H01L21/76898 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/7787 , H01L29/812
摘要： A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, metallizing the via provides an electrical path from the first surface of the substrate to the metal contact and to the device on the second surface of the substrate.
摘要翻译：公开了一种在碳化硅衬底上制造集成电路的方法，其消除了否则会导致不期望的电感的引线接合。该方法包括在硅碳化物衬底的表面上制造外延层中的半导体器件，并且在外延层的最上表面上具有用于器件的至少一个金属接触。然后将基板的相对表面研磨抛光直到基本透明。该方法然后包括掩盖碳化硅衬底的抛光表面，以限定用于至少一个通孔的预定位置，其与外延层的最上表面上的器件金属接触相对，并在步骤中蚀刻所需的通孔。第一蚀刻步骤在期望的掩蔽位置上蚀刻通过碳化硅衬底，直到蚀刻到达外延层。第二蚀刻步骤通过外延层蚀刻到器件触点。最后，通孔的金属化提供了从衬底的第一表面到金属接触件和衬底的第二表面上的器件的电路径。

9. 发明申请

US20070001174A1 Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides 有权
标题翻译：使用无氢溅射氮化物钝化宽带隙基半导体器件
公开(公告)号：US20070001174A1
公开(公告)日：2007-01-04
申请号：US11169378
申请日：2005-06-29
申请人： Zoltan Ring , Helmut Hagleitner , Jason Henning , Andrew Mackenzie , Scott Allen , Scott Sheppard , Richard Smith , Saptharishi Sriram , Allan Ward
发明人： Zoltan Ring , Helmut Hagleitner , Jason Henning , Andrew Mackenzie , Scott Allen , Scott Sheppard , Richard Smith , Saptharishi Sriram , Allan Ward
IPC分类号： H01L29/15 , H01L31/0256
CPC分类号： H01L21/045 , H01L21/3145 , H01L21/318 , H01L21/3185 , H01L29/1608 , H01L29/2003 , H01L29/24
摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.
摘要翻译：公开了钝化的半导体结构和相关方法。该结构包括碳化硅衬底或层; 在碳化硅衬底上的氧化层，用于降低碳化硅衬底和热氧化层之间的界面密度; 在热氧化层上的第一溅射的非化学计量的氮化硅层，用于减少寄生电容并最小化器件捕获; 在所述第一层上的第二溅射的非化学计量的氮化硅层，用于使所述衬底进一步从所述衬底定位以后的钝化层而不封装所述结构; 在第二溅射层上溅射化学计量的氮化硅层，用于封装该结构并增强钝化层的氢阻挡性能; 以及化学气相沉积的化学计量氮化硅的环境阻挡层，用于在封装层上进行步骤覆盖和防裂。

10. 发明授权

US10020244B2 Polymer via plugs with high thermal integrity 有权
公开(公告)号：US10020244B2
公开(公告)日：2018-07-10
申请号：US13431583
申请日：2012-03-27
申请人： Van Mieczkowski , Helmut Hagleitner , William T. Pulz
发明人： Van Mieczkowski , Helmut Hagleitner , William T. Pulz
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L2224/04026 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/29144 , H01L2924/0132 , H01L2924/10158 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/13064 , H01L2924/00 , H01L2924/0105 , H01L2924/01079 , H01L2924/01032 , H01L2924/01014
摘要： The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

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