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1. 发明授权

US09472284B2 Three-dimensional flash memory system 有权
标题翻译：三维闪存系统
公开(公告)号：US09472284B2
公开(公告)日：2016-10-18
申请号：US13680719
申请日：2012-11-19
申请人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C11/34 , G11C16/06 , G11C5/02 , G11C5/06 , G11C16/30 , G11C29/26 , G11C16/04 , G11C16/26 , G11C7/04 , G11C29/02 , G11C29/12 , H01L25/065 , H01L25/18
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

2. 发明授权

US08354864B2 Sense amplifier for low voltage high speed sensing 有权
公开(公告)号：US08354864B2
公开(公告)日：2013-01-15
申请号：US13286166
申请日：2011-10-31
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

3. 发明授权

US08067931B2 Fast voltage regulators for charge pumps 有权
公开(公告)号：US08067931B2
公开(公告)日：2011-11-29
申请号：US12987906
申请日：2011-01-10
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F3/26
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

4. 发明申请

US20110242921A1 Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features 有权
标题翻译：包括选择性/差分阈值电压特性的非易失性存储器感测的系统和方法
公开(公告)号：US20110242921A1
公开(公告)日：2011-10-06
申请号：US12750628
申请日：2010-03-30
申请人： Hieu Van Tran , Samar Saha
发明人： Hieu Van Tran , Samar Saha
IPC分类号： G11C7/06 , H01L29/792
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C16/28 , H01L21/28282 , H01L21/823412 , H01L21/823807 , H01L29/1083 , H01L29/42368 , H01L29/4238 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
摘要翻译：公开了用于通过使用具有差分阈值电压的MOS晶体管提供选择性阈值电压特性的系统和方法。在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压他们。

5. 发明申请

US20110169558A1 CHARGE PUMP SYSTEMS AND METHODS 有权
标题翻译：充电泵系统和方法
公开(公告)号：US20110169558A1
公开(公告)日：2011-07-14
申请号：US13070405
申请日：2011-03-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F1/10
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

6. 发明申请

US20110121863A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20110121863A1
公开(公告)日：2011-05-26
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G11C7/08 , H03F3/45 , G11C7/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

7. 发明申请

US20110121799A1 Fast Voltage Regulators For Charge Pumps 有权
标题翻译：用于充电泵的快速稳压器
公开(公告)号：US20110121799A1
公开(公告)日：2011-05-26
申请号：US12987906
申请日：2011-01-10
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/46 , G05F3/16 , G05F3/08
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

8. 发明授权

US07848159B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US07848159B2
公开(公告)日：2010-12-07
申请号：US12275191
申请日：2008-11-20
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

9. 发明申请

US20100142272A1 METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US20100142272A1
公开(公告)日：2010-06-10
申请号：US12629302
申请日：2009-12-02
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C16/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

10. 发明授权

US07729150B2 High-speed and low-power differential non-volatile content addressable memory cell and array 有权
标题翻译：高速和低功耗差分非易失性内容可寻址存储单元和阵列
公开(公告)号：US07729150B2
公开(公告)日：2010-06-01
申请号：US12176281
申请日：2008-07-18
申请人： Vishal Sarin , Hieu Van Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Van Tran , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
摘要翻译：差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制通道中的电子传导，以及控制栅极。浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动在第一端子和第二端子之间。一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

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