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1. 发明授权

US08539399B1 Method and apparatus for providing user-defined interfaces for a configurable processor 有权
标题翻译：用于为可配置处理器提供用户定义的接口的方法和装置
公开(公告)号：US08539399B1
公开(公告)日：2013-09-17
申请号：US11829063
申请日：2007-07-26
申请人： Nupur B. Andrews , James Kim , Himanshu A. Sanghavi , William A. Huffman , Eileen Margaret Peters Long
发明人： Nupur B. Andrews , James Kim , Himanshu A. Sanghavi , William A. Huffman , Eileen Margaret Peters Long
IPC分类号： G06F17/50
CPC分类号： G06F9/30101 , G06F9/30043 , G06F9/3826
摘要： A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware. This can have dramatic effects not only in the performance and bandwidth achieved by designs, but also in the time to market and reuse of such designs.
摘要翻译：一种通过可以添加到可配置和可扩展的微处理器内核的用户定义接口来提高处理器性能和相关数据带宽的技术。这些接口可用于传送状态或控制信息，并实现处理器与包括其他处理器在内的任何外部设备之间的同步。这些接口也可用于在每个时钟周期以每个接口的一个数据元素的速率实现数据传输。这种技术使得可以在不使用存储器子系统的情况下，在处理器之间设计具有高速数据传输的多处理器SOC系统。这种系统和设计方法提供了从基于标准总线的架构的全面转变，并允许设计人员将处理器视为真正的计算单元，从而使设计人员能够更有效地利用可编程解决方案，而不是设计专用硬件。这不仅可以在设计实现的性能和带宽方面，而且在上市时间和这种设计的再利用方面都会产生戏剧性的影响。

2. 发明授权

US07664928B1 Method and apparatus for providing user-defined interfaces for a configurable processor 有权
标题翻译：用于为可配置处理器提供用户定义的接口的方法和装置
公开(公告)号：US07664928B1
公开(公告)日：2010-02-16
申请号：US11039757
申请日：2005-01-19
申请人： Nupur B. Andrews , James Kim , Himanshu A. Sanghavi , William A. Huffman , Eileen Margaret Peters Long
发明人： Nupur B. Andrews , James Kim , Himanshu A. Sanghavi , William A. Huffman , Eileen Margaret Peters Long
IPC分类号： G06F15/00
CPC分类号： G06F9/30101 , G06F9/30043 , G06F9/3826
摘要： A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware. This can have dramatic effects not only in the performance and bandwidth achieved by designs, but also in the time to market and reuse of such designs.
摘要翻译：一种通过可以添加到可配置和可扩展的微处理器内核的用户定义接口来提高处理器性能和相关数据带宽的技术。这些接口可用于传送状态或控制信息，并实现处理器与包括其他处理器在内的任何外部设备之间的同步。这些接口也可用于在每个时钟周期以每个接口的一个数据元素的速率实现数据传输。这种技术使得可以在不使用存储器子系统的情况下，在处理器之间设计具有高速数据传输的多处理器SOC系统。这种系统和设计方法提供了从基于标准总线的架构的全面转变，并允许设计人员将处理器视为真正的计算单元，从而使设计人员能够更有效地利用可编程解决方案，而不是设计专用硬件。这不仅可以在设计实现的性能和带宽方面，而且在上市时间和这种设计的再利用方面都会产生戏剧性的影响。

3. 发明授权

US07376812B1 Vector co-processor for configurable and extensible processor architecture 有权
标题翻译：用于可配置和可扩展处理器架构的矢量协处理器
公开(公告)号：US07376812B1
公开(公告)日：2008-05-20
申请号：US10145380
申请日：2002-05-13
申请人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
发明人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30149 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/325 , G06F9/3816 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3893
摘要： A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
摘要翻译：处理器可以实现高代码密度，同时允许比现有架构更高的性能，特别是对于数字信号处理（DSP）应用。根据一个方面，处理器支持三种可能的指令大小，同时保持编程的简单性并且允许有效的物理实现。大多数应用程序代码可以使用两组窄尺寸指令进行编码，以实现较高的代码密度。添加第三个（即更大，即VLIW）指令大小允许架构对代码的性能关键部分的每个指令编码多个操作。此外，VLIW格式指令的每个操作可以可选地是对矢量数据进行操作的SIMD操作。还提供了用于乘法累加（MAC）硬件的最佳利用（给定量的硬件的最高可实现性能）的方案。

4. 发明授权

US07219212B1 Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion 有权
标题翻译：使用对准寄存器对存储器未对齐矢量数据进行加载/存储操作，存储重新排列的数据部分以与剩余部分组合
公开(公告)号：US07219212B1
公开(公告)日：2007-05-15
申请号：US11067106
申请日：2005-02-25
申请人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
发明人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
IPC分类号： G06F9/315
CPC分类号： G06F9/30149 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/325 , G06F9/3816 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3893
摘要： A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
摘要翻译：处理器可以实现高代码密度，同时允许比现有架构更高的性能，特别是对于数字信号处理（DSP）应用。根据一个方面，处理器支持三种可能的指令大小，同时保持编程的简单性并且允许有效的物理实现。大多数应用程序代码可以使用两组窄尺寸指令进行编码，以实现较高的代码密度。添加第三个（即更大，即VLIW）指令大小允许架构对代码的性能关键部分的每个指令编码多个操作。此外，VLIW格式指令的每个操作可以可选地是对矢量数据进行操作的SIMD操作。还提供了用于乘法累加（MAC）硬件的最佳利用（给定量的硬件的最高可实现性能）的方案。

5. 发明授权

US07184450B1 System and method for decoding audio/video data such as DVD or/and DVB data 有权
标题翻译：用于解码诸如DVD或/和DVB数据的音频/视频数据的系统和方法
公开(公告)号：US07184450B1
公开(公告)日：2007-02-27
申请号：US09301438
申请日：1999-04-28
申请人： Christopher K. Wolf , Ygal Arbel , Himanshu A. Sanghavi
发明人： Christopher K. Wolf , Ygal Arbel , Himanshu A. Sanghavi
IPC分类号： H04J3/04 , H04L12/28 , H04N5/91 , H04N5/262
CPC分类号： H04N21/434 , G11B20/10 , G11B20/10527 , G11B20/1403 , G11B27/3027 , G11B2020/10685 , G11B2020/10694 , G11B2220/2562 , H04J3/0638 , H04L69/12 , H04N21/23406 , H04N21/2368 , H04N21/42607 , H04N21/4341 , H04N21/44004
摘要： A system (20) for decoding a data stream allocated into data packets contains a control unit (54), a stream demultiplexer (26), audio and video decoders (38 and 40), a memory management unit (60), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.
摘要翻译：用于解码分配到数据分组中的数据流的系统（20）包括控制单元（54），流解复用器（26），音频和视频解码器（38和40），存储器管理单元（60）视频输入和输出缓冲区。在不中断控制单元的情况下对数据分组进行解复用和解封装，解复用器将编码的音频和视频数据发送到音频和视频输入缓冲器。视频消息处理视频定时信息并识别编码视频数据存储在视频输入缓冲器中的位置由解复用器提供，供控制单元使用。利用从控制单元提供的相应的视频指令，视频解码器解码编码的视频数据，产生提供给视频输出缓冲器的解码视频数据。音频解码器解码编码的音频数据以产生提供给音频输出缓冲器的解码音频数据。存储器管理单元控制向/从音频输出缓冲器的解码音频数据的传送。

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