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1. 发明申请

US20050278713A1 Automatic instruction set architecture generation 有权
公开(公告)号：US20050278713A1
公开(公告)日：2005-12-15
申请号：US11208239
申请日：2005-08-18
申请人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
发明人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

2. 发明申请

US20140182783A1 Two-Liquid Process for Synthesizing Polyurethane with High Heat-Resistance and High Abrasion-Resistance 审中-公开
标题翻译：用于合成具有高耐热性和高耐磨性的聚氨酯的双液体方法
公开(公告)号：US20140182783A1
公开(公告)日：2014-07-03
申请号：US13733191
申请日：2013-01-03
申请人： June-Chiarn Lee , Peng-Tu Yeh
发明人： June-Chiarn Lee , Peng-Tu Yeh
IPC分类号： B05D7/00
CPC分类号： B05D1/34 , B05D2252/02 , C08G18/10 , C08G18/80 , C08G2150/60 , C09D175/04 , D06N3/0047 , D06N3/0097 , D06N3/14 , D06N2211/28 , Y02P20/582
摘要： A two-liquid process for synthesizing polyurethane with high heat-resistance and high abrasion-resistance is disclosed, which utilizes a semi-reactive polymer A solution containing hydroxyl groups and a semi-reactive polymer B solution containing poly-isocyanate groups. The polymer A and B solution are mixed for performing a second reaction and then coated on a substrate by a coating machine, and the coating layer is cured to form a polyurethane film. The semi-reactive polymer A and B solution are pre-polymerized in advance. The required polyurethane resin expands on the semi-reactive polymer A and B with a whole range of new functionality and construction styles through polymerization to produce high heat-resistant and high abrasion-resistant polyurethane film through coating facility under the working temperature about 80° C. A fabric is coupled during coating step for polyurethane leather. The two-liquid process is without using solvent as carrier. The environmental problem of air and water pollution can be resolved.
摘要翻译：公开了一种用于合成具有高耐热性和高耐磨性的聚氨酯的双液体方法，其利用含有羟基的半反应性聚合物A溶液和含有聚异氰酸酯基团的半反应性聚合物B溶液。将聚合物A和B溶液混合以进行第二反应，然后通过涂布机涂布在基材上，并使涂层固化以形成聚氨酯膜。半反应性聚合物A和B溶液预先进行预聚合。所需的聚氨酯树脂在半反应性聚合物A和B上通过聚合在整个范围内具有全新的功能和结构形式，通过涂覆设备在约80℃的工作温度下生产高耐热和高耐磨性的聚氨酯膜在聚氨酯皮革的涂布步骤中将织物连接在一起。双液体方法不使用溶剂作为载体。空气和水污染的环境问题可以解决。

3. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

4. 发明授权

US06301704B1 Method, system, and computer program product for using static single assignment form as a program representation and a medium for performing global scalar optimization 失效
标题翻译：使用静态单一分配形式作为程序表示的方法，系统和计算机程序产品以及用于执行全局标量优化的介质
公开(公告)号：US06301704B1
公开(公告)日：2001-10-09
申请号：US09097672
申请日：1998-06-16
申请人： Frederick Chow , Sun Chan , Peter Dahl , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Mark Streich , Peng Tu
发明人： Frederick Chow , Sun Chan , Peter Dahl , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Mark Streich , Peng Tu
IPC分类号： G06F9445
CPC分类号： G06F8/443
摘要： A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.
摘要翻译：方法，系统和计算机产品使用散列静态单赋值（SSA）形式作为程序表示和用于执行全局标量优化的介质。在以SSA形式表达计算机程序之后，编译器可以在SSA表示上执行一个或多个基于静态单一分配（SSA）的SSA保留的全局标量优化过程。这样的过程修改（即优化）程序的SSA表示，同时保留其嵌入的使用 - 解除程序信息的用途，以用于随后的基于SSA的SSA保留的全局标量优化。这节省了为连续的基于SSA，保持SSA的全局标量优化显式地重新生成use-def程序信息的开销费用。

5. 发明授权

US06941548B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US06941548B2
公开(公告)日：2005-09-06
申请号：US09981291
申请日：2001-10-16
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

6. 发明授权

US6026241A System, method, and computer program product for partial redundancy elimination based on static single assignment form during compilation 失效
标题翻译：编译过程中基于静态单个分配表的部分冗余消除的系统，方法和计算机程序产品
公开(公告)号：US6026241A
公开(公告)日：2000-02-15
申请号：US873895
申请日：1997-06-13
申请人： Frederick Chow , Sun Chan , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Peng Tu
发明人： Frederick Chow , Sun Chan , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Peng Tu
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： Partial redundancy elimination of a computer program is described that operates using a static single assignment (SSA) representation of a computer program. The SSA representation of the computer program is processed to eliminate partially redundant expressions in the computer program. This processing involves inserting .PHI. functions for expressions where different values of the expressions reach common points in the computer program. A result of each of the .PHI. functions is stored in a hypothetical variable h. The processing also involves a renaming step where SSA versions are assigned to hypothetical variables h in the computer program, a down safety step of determining whether each .PHI. function in the computer program is down safe, and a will be available step of determining whether each expression in the computer program will be available at each .PHI. function following eventual insertion of code into the computer program for purposes of partial redundancy elimination. The processing also includes a finalize step of transforming the SSA representation of the computer program having hypothetical variables h to a SSA graph that includes some insertion information reflecting eventual insertions of code into the computer program for purposes of partial redundancy elimination, and a code motion step of updating the SSA graph based on the insertion information to introduce real temporary variables t for the hypothetical variables h.
摘要翻译：描述了使用计算机程序的静态单一分配（SSA）表示来操作计算机程序的部分冗余消除。处理计算机程序的SSA表示以消除计算机程序中的部分冗余表达式。该处理涉及为表达式插入PHI函数，其中表达式的不同值达到计算机程序中的公共点。每个PHI函数的结果存储在假设变量h中。该处理还包括重新命名步骤，其中SSA版本被分配给计算机程序中的假想变量h，确定计算机程序中的每个PHI功能是否下降的安全步骤，以及将是可用的步骤，确定每个表达式为了部分冗余消除的目的，在计算机程序中将最终将代码插入计算机程序之后，在每个PHI功能中将可用。该处理还包括将具有假设变量h的计算机程序的SSA表示形式的SSA图形变换为SSA图的最终确定步骤，该SSA图形包括反映最终插入代码到计算机程序中以便部分冗余消除的目的的一些插入信息，以及代码运动步骤基于插入信息更新SSA图，以为假设变量h引入真实临时变量t。

7. 发明授权

US07971197B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US07971197B2
公开(公告)日：2011-06-28
申请号：US11208239
申请日：2005-08-18
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/45 , G06F15/00 , G06F15/76
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

8. 发明授权

US07376812B1 Vector co-processor for configurable and extensible processor architecture 有权
标题翻译：用于可配置和可扩展处理器架构的矢量协处理器
公开(公告)号：US07376812B1
公开(公告)日：2008-05-20
申请号：US10145380
申请日：2002-05-13
申请人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
发明人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30149 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/325 , G06F9/3816 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3893
摘要： A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
摘要翻译：处理器可以实现高代码密度，同时允许比现有架构更高的性能，特别是对于数字信号处理（DSP）应用。根据一个方面，处理器支持三种可能的指令大小，同时保持编程的简单性并且允许有效的物理实现。大多数应用程序代码可以使用两组窄尺寸指令进行编码，以实现较高的代码密度。添加第三个（即更大，即VLIW）指令大小允许架构对代码的性能关键部分的每个指令编码多个操作。此外，VLIW格式指令的每个操作可以可选地是对矢量数据进行操作的SIMD操作。还提供了用于乘法累加（MAC）硬件的最佳利用（给定量的硬件的最高可实现性能）的方案。

9. 发明授权

US07219212B1 Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion 有权
标题翻译：使用对准寄存器对存储器未对齐矢量数据进行加载/存储操作，存储重新排列的数据部分以与剩余部分组合
公开(公告)号：US07219212B1
公开(公告)日：2007-05-15
申请号：US11067106
申请日：2005-02-25
申请人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
发明人： Himanshu A. Sanghavi , Earl A. Killian , James Robert Kennedy , Darin S. Petkov , Peng Tu , William A. Huffman
IPC分类号： G06F9/315
CPC分类号： G06F9/30149 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/325 , G06F9/3816 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3893
摘要： A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
摘要翻译：处理器可以实现高代码密度，同时允许比现有架构更高的性能，特别是对于数字信号处理（DSP）应用。根据一个方面，处理器支持三种可能的指令大小，同时保持编程的简单性并且允许有效的物理实现。大多数应用程序代码可以使用两组窄尺寸指令进行编码，以实现较高的代码密度。添加第三个（即更大，即VLIW）指令大小允许架构对代码的性能关键部分的每个指令编码多个操作。此外，VLIW格式指令的每个操作可以可选地是对矢量数据进行操作的SIMD操作。还提供了用于乘法累加（MAC）硬件的最佳利用（给定量的硬件的最高可实现性能）的方案。

10. 发明授权

US06128775A Method, system, and computer program product for performing register promotion via load and store placement optimization within an optimizing compiler 失效
标题翻译：方法，系统和计算机程序产品，用于通过优化编译器中的加载和存储放置优化来执行注册促进
公开(公告)号：US06128775A
公开(公告)日：2000-10-03
申请号：US97713
申请日：1998-06-16
申请人： Frederick Chow , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Peng Tu , Sun C. Chan
发明人： Frederick Chow , Robert Kennedy , Shin-Ming Liu , Raymond Lo , Peng Tu , Sun C. Chan
IPC分类号： G06F9/45
CPC分类号： G06F8/441 , G06F8/443
摘要： A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results. A static single use (SSU) representation is defined allowing the dual of the SSAPRE algorithm, called SSUPRE, to perform the partial redundancy elimination of stores. SSUPRE is performed after the PRE of loads, taking advantage of the loads' having been converted into pseudo-register references so that there are fewer barriers to the movement of stores. Consequently, the compiler produces more efficient, register-promoted executable program code from the SSA representation.
摘要翻译：一种用于执行注册促进的方法，系统和计算机程序产品，其优化了编译器内的计算机程序的加载和存储操作的布局。基于这样一种观察，即为了提升存储器位置的寄存器值的情况与存储单元存取位置之间存在部分冗余的情况相一致，系统是将优化模型化为两个独立问题的注册升级方法：（1 ）负载的部分冗余消除（PRE）和（2）存储的PRE。这两个问题都是通过稀疏的PRE方法解决的。使用稀疏SSA表示消除部分冗余的静态单分配PRE（SSAPRE）方法表示在消除存储器访问之间的冗余的基础上，使得能够在注册促进结果中实现计算和实时范围最优化。定义了静态单用（SSU）表示，允许称为SSUPRE的SSAPRE算法的双重性来执行商店的部分冗余消除。 SSUPRE在负载的PRE之后执行，利用已经转换为伪寄存器引用的负载，使得存储器移动的障碍较少。因此，编译器从SSA表示形成更高效的注册升级可执行程序代码。

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