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1. 发明申请

US20130322155A1 VARIABLE RESISTANCE MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME 有权
标题翻译：可变电阻存储器件和包括其的数据存储器件
公开(公告)号：US20130322155A1
公开(公告)日：2013-12-05
申请号：US13590763
申请日：2012-08-21
申请人： Chang Yong AHN , Ho Seok EM
发明人： Chang Yong AHN , Ho Seok EM
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0002 , G11C13/0061 , G11C13/0069 , G11C13/0097
摘要： A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.
摘要翻译：可变电阻存储器件包括布置在字线和位线彼此交叉的区域的存储单元，控制逻辑被配置为响应于从外部设备提供的程序命令产生指示程序操作模式的命令标志，基于所述命令标志来控制所述存储器单元的编程操作，以及配置为响应于所述标志命令被激活的写入驱动器，并且被配置为向所述存储器单元提供编程电流。

2. 发明授权

US08045368B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08045368B2
公开(公告)日：2011-10-25
申请号：US12345949
申请日：2008-12-30
申请人： Ho-Seok Em
发明人： Ho-Seok Em
IPC分类号： G11C11/00
CPC分类号： G11C8/18 , G11C8/04 , G11C13/0004 , G11C13/0069 , G11C2013/0085
摘要： A phase-change memory device performs a buffer program operation in response to a buffer program command sequence. The phase-change memory device includes a page buffer unit configured to store a plurality of input data corresponding to a word count value of a buffer program command sequence and selectively output the stored input data in response to a selection signal, and a page buffer control unit configured to generate the selection signal determined by counting a value representing the word count value.
摘要翻译：相变存储器件响应于缓冲器程序命令序列执行缓冲器程序操作。相变存储器件包括：页缓冲器单元，被配置为存储对应于缓冲器程序命令序列的字计数值的多个输入数据，并且响应于选择信号选择性地输出存储的输入数据;以及页缓冲器控制单元，被配置为生成通过对表示字计数值的值进行计数而确定的选择信号。

3. 发明授权

US08848420B2 Variable resistance memory device and data storage device including the same 有权
标题翻译：可变电阻存储器件和包括其的数据存储器件
公开(公告)号：US08848420B2
公开(公告)日：2014-09-30
申请号：US13590763
申请日：2012-08-21
申请人： Chang Yong Ahn , Ho Seok Em
发明人： Chang Yong Ahn , Ho Seok Em
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0002 , G11C13/0061 , G11C13/0069 , G11C13/0097
摘要： A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.
摘要翻译：可变电阻存储器件包括布置在字线和位线彼此交叉的区域的存储单元，控制逻辑被配置为响应于从外部设备提供的程序命令产生指示程序操作模式的命令标志，基于所述命令标志来控制所述存储器单元的编程操作，以及配置为响应于所述标志命令被激活的写入驱动器，并且被配置为向所述存储器单元提供编程电流。

4. 发明申请

US20110182114A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110182114A1
公开(公告)日：2011-07-28
申请号：US12827901
申请日：2010-06-30
申请人： Ho Seok Em , Dong Keun Kim
发明人： Ho Seok Em , Dong Keun Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/1048 , G11C7/12 , G11C8/14 , G11C13/0004 , G11C13/0026 , G11C13/02
摘要： A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.
摘要翻译：半导体存储器件基本上防止在读取操作中产生故障操作，并且增加了操作可靠性。该半导体存储器件包括一个单元阵列，其被配置为包括响应于数据具有不同电阻值的存储元件，被配置为感测和放大数据的感测放大器，被配置为将感测放大器耦合到单元的全局位线阵列和放电单元，其被配置为在执行读取操作之前对全局位线进行放电。

5. 发明授权

US08441845B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08441845B2
公开(公告)日：2013-05-14
申请号：US12827901
申请日：2010-06-30
申请人： Ho Seok Em , Dong Keun Kim
发明人： Ho Seok Em , Dong Keun Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/1048 , G11C7/12 , G11C8/14 , G11C13/0004 , G11C13/0026 , G11C13/02
摘要： A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.
摘要翻译：半导体存储器件基本上防止在读取操作中产生故障操作，并且增加了操作可靠性。该半导体存储器件包括一个单元阵列，其被配置为包括响应于数据具有不同电阻值的存储元件，被配置为感测和放大数据的感测放大器，被配置为将感测放大器耦合到单元的全局位线阵列和放电单元，其被配置为在执行读取操作之前对全局位线进行放电。

6. 发明授权

US08369138B2 Semiconductor memory device for reading out data stored in memory 有权
标题翻译：用于读出存储在存储器中的数据的半导体存储器件
公开(公告)号：US08369138B2
公开(公告)日：2013-02-05
申请号：US12828090
申请日：2010-06-30
申请人： Ho Seok Em , Taek Seung Kim
发明人： Ho Seok Em , Taek Seung Kim
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C29/02 , G11C2029/1202 , G11C2029/5006
摘要： A semiconductor memory device measures a leakage current generated when a unit cell is accessed during a test process. The semiconductor memory device includes a unit cell configured to include a memory element, a word line configured to be coupled to one end of the unit cell, and a bit line configured to be coupled to the other end of the unit cell. In a normal operation, a current signal flows from the bit line to the word line through the unit cell such that data stored in the memory element is read. In a test operation, the word line is deactivated and a read operation is carried out such that data stored in the memory element is read.
摘要翻译：半导体存储器件测量在测试过程中访问单位单元时产生的漏电流。半导体存储器件包括：单元单元，被配置为包括存储元件，被配置为耦合到单位单元的一端的字线以及被配置为耦合到单位单元的另一端的位线。在正常操作中，电流信号通过单位单元从位线流到字线，从而读出存储在存储元件中的数据。在测试操作中，字线被去激活，并且执行读取操作，使得存储在存储器元件中的数据被读取。

7. 发明申请

US20110157968A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110157968A1
公开(公告)日：2011-06-30
申请号：US12828090
申请日：2010-06-30
申请人： Ho Seok EM , Taek Seung KIM
发明人： Ho Seok EM , Taek Seung KIM
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C29/02 , G11C2029/1202 , G11C2029/5006
摘要： A semiconductor memory device measures a leakage current generated when a unit cell is accessed during a test process. The semiconductor memory device includes a unit cell configured to include a memory element, a word line configured to be coupled to one end of the unit cell, and a bit line configured to be coupled to the other end of the unit cell. In a normal operation, a current signal flows from the bit line to the word line through the unit cell such that data stored in the memory element is read. In a test operation, the word line is deactivated and a read operation is carried out such that data stored in the memory element is read.
摘要翻译：半导体存储器件测量在测试过程中访问单位单元时产生的漏电流。半导体存储器件包括：单元单元，被配置为包括存储元件，被配置为耦合到单位单元的一端的字线以及被配置为耦合到单位单元的另一端的位线。在正常操作中，电流信号通过单位单元从位线流到字线，从而读出存储在存储元件中的数据。在测试操作中，字线被去激活，并且执行读取操作，使得存储在存储器元件中的数据被读取。

8. 发明申请

US20100149860A1 PHASE-CHANGE MEMORY DEVICE 有权
标题翻译：相变存储器件
公开(公告)号：US20100149860A1
公开(公告)日：2010-06-17
申请号：US12345949
申请日：2008-12-30
申请人： Ho-Seok EM
发明人： Ho-Seok EM
IPC分类号： G11C11/00 , G11C8/18 , G11C7/00
CPC分类号： G11C8/18 , G11C8/04 , G11C13/0004 , G11C13/0069 , G11C2013/0085
摘要： A phase-change memory device performs a buffer program operation in response to a buffer program command sequence. The phase-change memory device includes a page buffer unit configured to store a plurality of input data corresponding to a word count value of a buffer program command sequence and selectively output the stored input data in response to a selection signal, and a page buffer control unit configured to generate the selection signal determined by counting a value representing the word count value.
摘要翻译：相变存储器件响应于缓冲器程序命令序列执行缓冲器程序操作。相变存储器件包括：页缓冲器单元，被配置为存储对应于缓冲器程序命令序列的字计数值的多个输入数据，并且响应于选择信号选择性地输出存储的输入数据;以及页缓冲器控制单元，被配置为生成通过对表示字计数值的值进行计数而确定的选择信号。

9. 发明授权

US08476937B2 Input buffer circuit capable of adjusting variation in skew 有权
标题翻译：输入缓冲电路，能够调整偏差变化
公开(公告)号：US08476937B2
公开(公告)日：2013-07-02
申请号：US12980288
申请日：2010-12-28
申请人： Ho Seok Em
发明人： Ho Seok Em
IPC分类号： H03K5/22 , H03K5/153
CPC分类号： G11C29/02 , G11C7/1078 , G11C7/1084 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03K19/018514
摘要： An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.
摘要翻译：一种用于半导体器件的输入缓冲电路，包括比较器，用于将参考电压与输入信号的电压进行比较，并输出比较结果;激活单元，配置为响应于输入缓冲器的响应，控制输入缓冲器的激活状态使能信号，歪斜调整单元，被配置为响应于一个或多个偏斜调整信号而改变在比较器中流动的电流量;以及控制信号发生器，被配置为响应于一个控制信号来控制使能信号和歪斜调整信号或更多的校准代码和输入控制信号。

10. 发明申请

US20110316604A1 INPUT BUFFER CIRCUIT 有权
标题翻译：输入缓冲电路
公开(公告)号：US20110316604A1
公开(公告)日：2011-12-29
申请号：US12980288
申请日：2010-12-28
申请人： Ho Seok EM
发明人： Ho Seok EM
IPC分类号： H03L5/00
CPC分类号： G11C29/02 , G11C7/1078 , G11C7/1084 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03K19/018514
摘要： An input buffer circuit for use in a semiconductor device includes a comparator configured to compare a reference voltage with a voltage of an input signal, and output the result of comparison, an activation unit configured to control an activation state of an input buffer in response to an enable signal, a skew adjusting unit configured to change an amount of a current flowing in the comparator in response to one or more skew adjusting signals, and a control signal generator configured to control the enable signal and the skew adjusting signal in response to one or more calibration codes and an input control signal.
摘要翻译：一种用于半导体器件的输入缓冲电路，包括比较器，用于将参考电压与输入信号的电压进行比较，并输出比较结果;激活单元，配置为响应于输入缓冲器的响应，控制输入缓冲器的激活状态使能信号，歪斜调整单元，被配置为响应于一个或多个偏斜调整信号而改变在比较器中流动的电流量;以及控制信号发生器，被配置为响应于一个控制信号来控制使能信号和歪斜调整信号或更多的校准代码和输入控制信号。

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