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1. 发明授权

US08134211B2 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US08134211B2
公开(公告)日：2012-03-13
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

2. 发明授权

US07285458B2 Method for forming an ESD protection circuit 有权
标题翻译： ESD保护电路的形成方法
公开(公告)号：US07285458B2
公开(公告)日：2007-10-23
申请号：US10776793
申请日：2004-02-11
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L21/8234
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

3. 发明申请

US20070085142A1 TUNABLE PROTECTION SYSTEM FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路保护系统
公开(公告)号：US20070085142A1
公开(公告)日：2007-04-19
申请号：US11163349
申请日：2005-10-15
申请人： Indrajit Manna , Hin Yap , Keng Lo , Jae Park
发明人： Indrajit Manna , Hin Yap , Keng Lo , Jae Park
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.
摘要翻译：一种可调谐保护系统，包括形成提供可调保护激活电平的可调谐触发装置，形成为集成电路提供保护的电路保护装置，以及将可调谐触发装置和电路保护装置电连接到输入/输出垫。

4. 发明申请

US20060081933A1 Electrostatic discharge protection device with complementary dual drain implant 有权
公开(公告)号：US20060081933A1
公开(公告)日：2006-04-20
申请号：US11291757
申请日：2005-12-01
申请人： Indrajit Manna , Keng Lo , Pee Tan , Michael Cheng
发明人： Indrajit Manna , Keng Lo , Pee Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

5. 发明授权

US06998685B2 Electrostatic discharge protection device with complementary dual drain implant 有权
标题翻译：具有互补双漏极植入物的静电放电保护器件
公开(公告)号：US06998685B2
公开(公告)日：2006-02-14
申请号：US10662673
申请日：2003-09-15
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.
摘要翻译：具有ESD保护的片外驱动器（OCD）NMOS晶体管通过在OCD NMOS晶体管的N +漏极区域和N阱之间插入P-ESD注入而形成，使得P-ESD围绕N阱的一部分。 P-ESD植入物的剂量小于N +源/漏植入物，但高于N阱剂量。在另一个实施例中，使用N阱掺杂以及P-ESD掺杂，其中选择P-ESD掺杂使得其对N +漏极下方的N阱进行反向。然而，N阱仍然保持与N +排水管的电气连接。该过程在结点发生的区域下面形成较大的表面，并且连接部的曲率半径增加。 P-ESD植入体在三面覆盖N型，产生更好的寄生双极晶体管特性。

6. 发明授权

US06936895B2 ESD protection device 失效
标题翻译： ESD保护装置
公开(公告)号：US06936895B2
公开(公告)日：2005-08-30
申请号：US10682055
申请日：2003-10-09
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
IPC分类号： H01L21/425 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L29/49 , H01L29/868 , H01L31/075
CPC分类号： H01L29/4983 , H01L27/0255 , H01L27/0266 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
摘要翻译：实现了形成集成电路器件的新方法。该方法包括形成覆盖半导体衬底的电介质层。形成覆盖在介电层上的本征半导体层。本征半导体层被图案化。在本征半导体层中形成p +区。在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

7. 发明授权

US07135743B2 Electrostatic discharge protection device with complementary dual drain implant 有权
公开(公告)号：US07135743B2
公开(公告)日：2006-11-14
申请号：US11291757
申请日：2005-12-01
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Michael Cheng
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

8. 发明申请

US20050077577A1 Novel ESD protection device 失效
标题翻译：新型ESD保护装置
公开(公告)号：US20050077577A1
公开(公告)日：2005-04-14
申请号：US10682055
申请日：2003-10-09
申请人： Indrajit Manna , Keng Lo , Pee Tan , Raymond Filippi
发明人： Indrajit Manna , Keng Lo , Pee Tan , Raymond Filippi
IPC分类号： H01L21/425 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L29/49 , H01L29/868 , H01L31/075
CPC分类号： H01L29/4983 , H01L27/0255 , H01L27/0266 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
摘要翻译：实现了形成集成电路器件的新方法。该方法包括形成覆盖半导体衬底的电介质层。形成覆盖在介电层上的本征半导体层。本征半导体层被图案化。在本征半导体层中形成p +区。在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

9. 发明授权

US09165920B2 Tunable protection system for integrated circuits 有权
标题翻译：集成电路可调保护系统
公开(公告)号：US09165920B2
公开(公告)日：2015-10-20
申请号：US11163349
申请日：2005-10-15
申请人： Indrajit Manna , Hin Kiong Yap , Keng Foo Lo , Jae Soo Park
发明人： Indrajit Manna , Hin Kiong Yap , Keng Foo Lo , Jae Soo Park
IPC分类号： H01L29/66 , H01L23/62 , H01L29/02 , H01L29/06 , H01L23/58 , H01L27/02
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.
摘要翻译：一种可调谐保护系统，包括形成提供可调保护激活电平的可调谐触发装置，形成为集成电路提供保护的电路保护装置，以及将可调谐触发装置和电路保护装置电连接到输入/输出垫。

10. 发明申请

US20100001283A1 TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION 有权
标题翻译：用于射频ESD保护的触发硅控制整流器
公开(公告)号：US20100001283A1
公开(公告)日：2010-01-07
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L29/04 , H01L29/73
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

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