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1. 发明授权

US08134211B2 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US08134211B2
公开(公告)日：2012-03-13
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

2. 发明授权

US07285458B2 Method for forming an ESD protection circuit 有权
标题翻译： ESD保护电路的形成方法
公开(公告)号：US07285458B2
公开(公告)日：2007-10-23
申请号：US10776793
申请日：2004-02-11
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L21/8234
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

3. 发明申请

US20100001283A1 TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION 有权
标题翻译：用于射频ESD保护的触发硅控制整流器
公开(公告)号：US20100001283A1
公开(公告)日：2010-01-07
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L29/04 , H01L29/73
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

4. 发明申请

US20080001168A1 TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION 有权
标题翻译：用于射频ESD保护的触发硅控制整流器
公开(公告)号：US20080001168A1
公开(公告)日：2008-01-03
申请号：US11854104
申请日：2007-09-12
申请人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
IPC分类号： H01L29/74 , H01L21/332 , H01R43/00 , H02H9/00
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

5. 发明授权

US07064358B2 Triggered back-to-back diodes for ESD protection in triple-well CMOS process 失效
标题翻译：触发式背对背二极管，用于三阱CMOS工艺中的ESD保护
公开(公告)号：US07064358B2
公开(公告)日：2006-06-20
申请号：US10743596
申请日：2003-12-22
申请人： Indrajlt Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
发明人： Indrajlt Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
IPC分类号： H01L29/72
CPC分类号： H01L27/0259
摘要： An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.
摘要翻译：一个实施例是一种静电放电（ESD）保护装置，其包括：半导体结构中的p阱中的n掺杂区域和p掺杂区域。 n掺杂区域和p掺杂区域间隔开。围绕p-well的两侧和底部的n井和深n井。连接到n掺杂区域的第一I / O焊盘。连接第一I / O焊盘和p掺杂区域的触发电路。连接到n阱的第二个I / O焊盘。寄生双极晶体管由用作集电极端子的n掺杂区域，用作基极端子的P阱和用作发射极端子的深N阱组成。在ESD条件下，使用触发电路将p阱充电为正极，并且可以接通寄生双极晶体管。

6. 发明申请

US20050133870A1 Triggererd back-to-back diodes for ESD protection in triple-well CMOS process 失效
标题翻译：用于三阱CMOS工艺中的ESD保护的Triggererd背对背二极管
公开(公告)号：US20050133870A1
公开(公告)日：2005-06-23
申请号：US10743596
申请日：2003-12-22
申请人： Indrajlt Manna , Keng Lo , Pee Tan , Raymond Filippi
发明人： Indrajlt Manna , Keng Lo , Pee Tan , Raymond Filippi
IPC分类号： H01L23/62 , H01L27/02
CPC分类号： H01L27/0259
摘要： An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.
摘要翻译：一个实施例是一种静电放电（ESD）保护装置，其包括：半导体结构中的p阱中的n掺杂区域和p掺杂区域。 n掺杂区域和p掺杂区域间隔开。围绕p-well的两侧和底部的n井和深n井。连接到n掺杂区域的第一I / O焊盘。连接第一I / O焊盘和p掺杂区域的触发电路。连接到n阱的第二个I / O焊盘。寄生双极晶体管由用作集电极端子的n掺杂区域，用作基极端子的P阱和用作发射极端子的深N阱组成。在ESD条件下，使用触发电路将p阱充电为正极，并且可以接通寄生双极晶体管。

7. 发明授权

US08434038B2 Consistency check in device design and manufacturing 有权
标题翻译：一致性检查设备设计和制造
公开(公告)号：US08434038B2
公开(公告)日：2013-04-30
申请号：US12829408
申请日：2010-07-02
申请人： Raghunathann Ramakrishnan , Zia Ahmed , Raymond Filippi
发明人： Raghunathann Ramakrishnan , Zia Ahmed , Raymond Filippi
IPC分类号： G06F9/455
CPC分类号： G06F17/5081
摘要： A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有前端和后端信息的至少一个原始图稿文件。原始图稿文件包含原始图稿文件格式。对应于原始图稿文件的修改后的图稿文件以第一个修改后的图稿文件格式提供。修改后的图稿文件包含后端信息。该方法还包括检查以确保原始和修改的图稿文件是一致的。

8. 发明申请

US20120005633A1 CONSISTENCY CHECK IN DEVICE DESIGN AND MANUFACTURING 有权
标题翻译：一致检查设备设计和制造
公开(公告)号：US20120005633A1
公开(公告)日：2012-01-05
申请号：US12829408
申请日：2010-07-02
申请人： Raghunathann RAMAKRISHNAN , Zia AHMED , Raymond FILIPPI
发明人： Raghunathann RAMAKRISHNAN , Zia AHMED , Raymond FILIPPI
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有前端和后端信息的至少一个原始图稿文件。原始图稿文件包含原始图稿文件格式。对应于原始图稿文件的修改后的图稿文件以第一个修改后的图稿文件格式提供。修改后的图稿文件包含后端信息。该方法还包括检查以确保原始和修改的图稿文件是一致的。

9. 发明授权

US07615417B2 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US07615417B2
公开(公告)日：2009-11-10
申请号：US11854104
申请日：2007-09-12
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L21/332
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点和集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

10. 发明申请

US20050173727A1 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US20050173727A1
公开(公告)日：2005-08-11
申请号：US10776793
申请日：2004-02-11
申请人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
IPC分类号： H01L21/331 , H01L27/02 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

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