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1. 发明授权

US08134211B2 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US08134211B2
公开(公告)日：2012-03-13
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

2. 发明授权

US07285458B2 Method for forming an ESD protection circuit 有权
标题翻译： ESD保护电路的形成方法
公开(公告)号：US07285458B2
公开(公告)日：2007-10-23
申请号：US10776793
申请日：2004-02-11
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L21/8234
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

3. 发明申请

US20100001283A1 TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION 有权
标题翻译：用于射频ESD保护的触发硅控制整流器
公开(公告)号：US20100001283A1
公开(公告)日：2010-01-07
申请号：US12559401
申请日：2009-09-14
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L29/04 , H01L29/73
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译： ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

4. 发明授权

US07615417B2 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US07615417B2
公开(公告)日：2009-11-10
申请号：US11854104
申请日：2007-09-12
申请人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Keng Foo , Tan Pee Ya , Raymond Filippi
IPC分类号： H01L21/332
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点和集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

5. 发明授权

US06724214B2 Test structures for on-chip real-time reliability testing 有权
标题翻译：用于片上实时可靠性测试的测试结构
公开(公告)号：US06724214B2
公开(公告)日：2004-04-20
申请号：US10243392
申请日：2002-09-13
申请人： Indrajit Manna , Lo Keng Foo , Guo Qiang , Zeng Xu
发明人： Indrajit Manna , Lo Keng Foo , Guo Qiang , Zeng Xu
IPC分类号： G01R3126
CPC分类号： G01R31/2858 , G01R31/129 , G01R31/2642 , G01R31/2884 , G01R31/3004 , H01L22/34
摘要： A first on-chip test structure monitors hot carrier degradation. A degrading ring oscillator is subjected to hot carrier effects while a non-degrading ring oscillator is not. As the device ages, hot carrier effects degrade the degrading ring counter. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same that experienced by percentage of gates under normal usage. A drop in the resistance indicates breakdown of a capacitor. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied such that the time to failure of all metal lines is the same as that experienced by a percentage of minimum width metal lines under normal usage. An increase in resistance indicates breakdown of a metal line.
摘要翻译：第一个片上测试结构可以监测热载流子的劣化。降解环形振荡器经受热载流子效应，而不降解环形振荡器则不受影响。随着设备的老化，热载体效应会降低降级环计数器。第二个测试结构监测TDDB的退化。多个N个并联的电容器具有施加到它们的应力电压，使得第一电容器的故障时间与在正常使用下门的百分比相同。电阻的下降指示电容器的击穿。第三个测试结构监测电迁移退化。 M个最小宽度金属线并联连接。施加电流使得所有金属线的故障时间与正常使用下的最小宽度金属线的百分比所经历的时间相同。电阻的增加表示金属线的击穿。

6. 发明授权

US06842078B2 Ring oscillator with variable loading 失效
标题翻译：环形振荡器具有可变负载
公开(公告)号：US06842078B2
公开(公告)日：2005-01-11
申请号：US10403447
申请日：2003-03-31
申请人： Indrajit Manna , Lo Keng Foo
发明人： Indrajit Manna , Lo Keng Foo
IPC分类号： H03K3/03 , H03L7/099 , H03L7/18 , H03L7/00
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/18
摘要： A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.
摘要翻译：实现环形振荡器电路装置。该装置包括奇数个反相级。每个反相级具有输入端和输出端。反相器级以环形耦合，使得先前反相级的输出端耦合到后续反相级的输入端。包括可变电容器。可变电容器包括覆盖体半导体区域的导电层，其间具有介电层。导电层耦合到一个反相级的输出端。可变电容器的值取决于耦合到体半导体区域的体电压。环形振荡器用于分析热载流子注入的负载依赖性。环形振荡器用作锁相环电路中的压控振荡器。

7. 发明申请

US20050077577A1 Novel ESD protection device 失效
标题翻译：新型ESD保护装置
公开(公告)号：US20050077577A1
公开(公告)日：2005-04-14
申请号：US10682055
申请日：2003-10-09
申请人： Indrajit Manna , Keng Lo , Pee Tan , Raymond Filippi
发明人： Indrajit Manna , Keng Lo , Pee Tan , Raymond Filippi
IPC分类号： H01L21/425 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L29/49 , H01L29/868 , H01L31/075
CPC分类号： H01L29/4983 , H01L27/0255 , H01L27/0266 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
摘要翻译：实现了形成集成电路器件的新方法。该方法包括形成覆盖半导体衬底的电介质层。形成覆盖在介电层上的本征半导体层。本征半导体层被图案化。在本征半导体层中形成p +区。在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

8. 发明授权

US06936895B2 ESD protection device 失效
标题翻译： ESD保护装置
公开(公告)号：US06936895B2
公开(公告)日：2005-08-30
申请号：US10682055
申请日：2003-10-09
申请人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
发明人： Indrajit Manna , Keng Foo Lo , Pee Ya Tan , Raymond Filippi
IPC分类号： H01L21/425 , H01L21/8234 , H01L23/62 , H01L27/02 , H01L29/49 , H01L29/868 , H01L31/075
CPC分类号： H01L29/4983 , H01L27/0255 , H01L27/0266 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
摘要翻译：实现了形成集成电路器件的新方法。该方法包括形成覆盖半导体衬底的电介质层。形成覆盖在介电层上的本征半导体层。本征半导体层被图案化。在本征半导体层中形成p +区。在本征半导体层中形成n +区。 p +区域和所述n +区域被本征区域横向分开，从而形成PIN二极管器件。在半导体衬底中形成源极区和漏极区，从而完成MOSFET器件。 PIN二极管器件是用于MOSFET器件的栅电极。

9. 发明申请

US20080001168A1 TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION 有权
标题翻译：用于射频ESD保护的触发硅控制整流器
公开(公告)号：US20080001168A1
公开(公告)日：2008-01-03
申请号：US11854104
申请日：2007-09-12
申请人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
IPC分类号： H01L29/74 , H01L21/332 , H01R43/00 , H02H9/00
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

10. 发明申请

US20050173727A1 Triggered silicon controlled rectifier for RF ESD protection 有权
标题翻译：触发的可控硅整流器用于射频ESD保护
公开(公告)号：US20050173727A1
公开(公告)日：2005-08-11
申请号：US10776793
申请日：2004-02-11
申请人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
发明人： Indrajit Manna , Lo Foo , Tan Ya , Raymond Filippi
IPC分类号： H01L21/331 , H01L27/02 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
摘要翻译：在集成电路的输入/输出接口触点处形成ESD保护电路，以保护集成电路免受ESD事件的损害。 ESD保护电路具有连接在集成电路的信号输入/输出接口触点与集成电路的电源连接和偏置电路之间的多晶硅界限SCR。偏置电路连接到多晶硅限制的SCR以偏置多晶硅界定的SCR，以在ESD事件期间更快地导通。偏置电路由至少一个多晶硅界限二极管和第一电阻形成。偏置电路的其它实施例包括电阻/电容器偏置电路和第二二极管触发偏置电路。

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