专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08164495B2 Integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACS) 有权
标题翻译：用于数模转换器（DACS）的集成非线性（INL）和差分非线性（DNL）校正技术
公开(公告)号：US08164495B2
公开(公告)日：2012-04-24
申请号：US12877904
申请日：2010-09-08
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/06
CPC分类号： H03M1/1052 , H03M1/66
摘要： INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
摘要翻译：针对适于接受N位数字输入代码的DAC的多个子段确定INL值，以及第一组校正代码，其可用于减少到INL值的范围（从而提高线性度 DAC）被确定并存储。另外，对于确定了INL值的多个子段确定DNL值，以及第二组校正码，可用于确保DNL> -1的所有值（从而确保DAC是单调的）被确定并存储。这可以包括使用一个或多个额外的分辨率来将至少一些可能的数字输入代码（可被DAC接受）重新映射到超过2 ^ N个可能的数字输出代码，以确保所有值 DNL> -1。此后，在进行数模转换时使用这样存储的第一和第二组。

2. 发明申请

US20120161992A1 INTEGRATED NON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS) 有权
标题翻译：用于数字到模拟转换器（DACS）的集成非线性（INL）和差分非线性（DNL）校正技术
公开(公告)号：US20120161992A1
公开(公告)日：2012-06-28
申请号：US13411253
申请日：2012-03-02
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/06
CPC分类号： H03M1/1052 , H03M1/66
摘要： INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2̂N possible digital input codes (that can be accepted by the DAC) to more than 2̂N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
摘要翻译：确定适用于接受N位数字输入代码的DAC的子段的INL值，并且确定可用于减小到INL值的范围（以提高DAC的线性度）的第一组校正码，并且存储。另外，为DAC的子段确定DNL值，还可以使用第二组校正码来确定并保存DNL> -1的所有值（以确保DAC是单调的）。这可以包括使用一个或多个额外的分辨率来将2N个可能的数字输入代码（可被DAC接受）中的至少一些重新映射到超过2N个可能的数字输出代码，以确保所有DNL> 1。此后，在进行数模转换时使用这样存储的第一和第二组。

3. 发明申请

US20110109487A1 INTEGRATED NON-LINEARITY (INL) AND DIFFERENTIAL NON-LINEARITY (DNL) CORRECTION TECHNIQUES FOR DIGITAL-TO-ANALOG CONVERTERS (DACS) 有权
标题翻译：用于数字到模拟转换器（DACS）的集成非线性（INL）和差分非线性（DNL）校正技术
公开(公告)号：US20110109487A1
公开(公告)日：2011-05-12
申请号：US12877904
申请日：2010-09-08
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/10
CPC分类号： H03M1/1052 , H03M1/66
摘要： INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL >−1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2̂N possible digital input codes (that can be accepted by the DAC) to more than 2̂N possible digital output codes, to ensure that all values of DNL >−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
摘要翻译：针对适于接受N位数字输入码的DAC的多个子段确定INL值，以及第一组校正码，其可用于减少到INL值的范围（从而提高线性度 DAC）被确定并存储。另外，对于确定了INL值的多个子段确定DNL值，以及第二组校正码，可用于确保DNL> -1的所有值（从而确保DAC是单调的）被确定并存储。这可以包括使用一个或多个额外的分辨率来将2N个可能的数字输入代码（可被DAC接受）中的至少一些重新映射到超过2N个可能的数字输出代码，以确保所有DNL> 1。此后，在进行数模转换时使用这样存储的第一和第二组。

4. 发明授权

US08564463B2 Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) correction techniques for digital-to-analog converters (DACS) 有权
标题翻译：用于数模转换器（DACS）的集成非线性（INL）和差分非线性（DNL）校正技术
公开(公告)号：US08564463B2
公开(公告)日：2013-10-22
申请号：US13411253
申请日：2012-03-02
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/06
CPC分类号： H03M1/1052 , H03M1/66
摘要： INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
摘要翻译：确定适用于接受N位数字输入代码的DAC的子段的INL值，并且确定可用于减小到INL值的范围（以提高DAC的线性度）的第一组校正码，并且存储。另外，为DAC的子段确定DNL值，以及第二组校正码，可用于确保DNL> -1的所有值（以确保DAC是单调的）的确定和存储。这可以包括使用一个或多个额外的分辨率来将至少一些可能的数字输入代码（可被DAC接受）重新映射到超过2 ^ N个可能的数字输出代码，以确保所有值 DNL> -1。此后，在进行数模转换时使用这样存储的第一和第二组。

5. 发明授权

US06404927B1 Control point generation and data packing for variable length image compression 失效
标题翻译：用于可变长度图像压缩的控制点生成和数据打包
公开(公告)号：US06404927B1
公开(公告)日：2002-06-11
申请号：US09268277
申请日：1999-03-15
申请人： Jun Li , Iskender Agi
发明人： Jun Li , Iskender Agi
IPC分类号： G06K936
CPC分类号： H03M7/46 , H03M7/42 , H04N1/648 , H04N11/042
摘要： A simple, cost-effective compression circuit which compress raw color data without interpolation. Control points common to all the colors in a line are generated each time one of the colors exceeds the color change threshold. The change in the other color is recorded at the same time even though it doesn't exceed the minimum change threshold.
摘要翻译：一种简单的，具有成本效益的压缩电路，可压缩未插值的原始颜色数据。每当一个颜色超过颜色变化阈值时，就会生成一行中所有颜色共同的控制点。即使不超过最小变化阈值，也会同时记录另一种颜色的变化。

6. 发明授权

US6127956A Post-conversion system for an analog-to-digital converter which sets an added bit of resolution if an intermediate sample is within a threshold 失效
标题翻译：用于模数转换器的后转换系统，如果中间采样在阈值内，则设置增加的分辨率位
公开(公告)号：US6127956A
公开(公告)日：2000-10-03
申请号：US108755
申请日：1998-07-01
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/20
CPC分类号： H03M1/20
摘要： Post processing of the converted digital bits from an ADC to provide one or more additional bits of resolution. The additional bits of resolution will be accurate for data which is locally correlated, such as image data. For a particular digital sample, a curve (such as a straight line) is fitted through adjacent samples to determine an expected value for the current sample. The actual digital sample is compared to the expected value to determine whether it is within a threshold of the expected value. The value of an additional bit of resolution is set based upon whether the sample is within the threshold.
摘要翻译：后处理ADC转换的数字位，以提供一个或多个额外的分辨率位。分辨率的附加位对于局部相关的数据（如图像数据）将是准确的。对于特定的数字样本，通过相邻样本拟合曲线（如直线），以确定当前样本的预期值。将实际数字样本与预期值进行比较，以确定其是否在预期值的阈值内。基于样本是否在阈值内设置附加位分辨率的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式