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1. 发明申请

US20190149161A1 TRANSMISSION DEVICE, TRANSMISSION SYSTEM, AND ROBOT 审中-公开
公开(公告)号：US20190149161A1
公开(公告)日：2019-05-16
申请号：US16307295
申请日：2017-05-16
申请人： Sony Corporation
发明人： Hiromasa MASUDA , Naoki KOMINE , Hirokazu YASUDA
IPC分类号： H03M1/20 , H03M9/00 , G06F13/42
CPC分类号： H03M1/20 , B25J19/00 , G06F13/4282 , H03M9/00
摘要： There is provided a transmission device configured to serialize data of a change amount that is based on a signal acquired from a sensor, and transmit the data by simplex communication.

2. 发明授权

US09484970B2 Analog-to-digital conversion with noise injection via wavefront multiplexing techniques 有权
公开(公告)号：US09484970B2
公开(公告)日：2016-11-01
申请号：US14988809
申请日：2016-01-06
申请人： SPATIAL DIGITAL SYSTEMS, INC.
发明人： Donald C. D. Chang , Tzer-Hso Lin , Yuanchang Liu
IPC分类号： H03M1/12 , H04B1/12 , H03M1/06 , H04B1/04 , H04B7/10 , H03M1/00 , H03M1/08 , H03M1/18 , H03M1/20 , H04L27/06
CPC分类号： H03M1/002 , H03M1/0641 , H03M1/08 , H03M1/12 , H03M1/1205 , H03M1/1215 , H03M1/188 , H03M1/20 , H04B1/0475 , H04B1/123 , H04B7/10 , H04L27/06
摘要： A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.

3. 发明申请

US20160156366A1 CAPACITIVE SENSING SYSTEM AND METHOD 有权
标题翻译：电容式感应系统及方法
公开(公告)号：US20160156366A1
公开(公告)日：2016-06-02
申请号：US14897854
申请日：2014-06-11
申请人： IEE INTERNATIONAL ELECTRONICS & ENGINEERING S.A.
发明人： Laurent LAMESCH
IPC分类号： H03M1/20 , H03M1/12 , H03C3/02
CPC分类号： H03M1/20 , H03C3/02 , H03M1/124 , H03M1/201
摘要： A capacitive sensing system operates according to a method which uses an ADC with a low resolution r, to produce a digital signal with a higher resolution R. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. Thereby, digital samples are produced. An average is taken over N (>1) successive digital samples. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≧1, of the quantization step size of the ADC. The saw-tooth or triangular signal, furthermore, has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.
摘要翻译：电容式感测系统根据使用具有低分辨率r的ADC的方法进行工作，以产生具有更高分辨率R的数字信号。要被数字化的模拟信号用三角形或锯齿调制信号调制，使得得到一个调制的模拟信号，用ADC进行采样。从而产生数字样本。 N（> 1）个连续数字样本的平均数。三角形或锯齿状信号被选择为具有至少近似于ADC的量化步长的L≥1的整数倍L的峰峰值幅度。此外，锯齿或三角形信号具有每个N个样本的每个序列的周期数M。 M和N被选择为使得M> 1且M≠N，并且使得R = r * N /（k * gcd（N，M）* L），其中gcd（M，N）是N的最大公约数如果调制信号是锯齿信号，则k = 2，如果调制信号是三角形信号，则k = 4。

4. 发明申请

US20160134297A1 METHOD AND DEVICE FOR ANALOG/DIGITAL CONVERSION OF AN ANALOG SIGNAL 有权
标题翻译：用于模拟信号的模拟/数字转换的方法和装置
公开(公告)号：US20160134297A1
公开(公告)日：2016-05-12
申请号：US14835980
申请日：2015-08-26
申请人： STMICROELECTRONICS (GRENOBLE 2) SAS
发明人： Laurent SIMONY
IPC分类号： H03M1/20 , H01L27/146 , H03M1/36 , H03M1/00 , H03M1/06
CPC分类号： H03M1/20 , H01L27/14643 , H03M1/002 , H03M1/0604 , H03M1/188 , H03M1/36 , H03M1/56
摘要： A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2n-m times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.
摘要翻译：一种方法包括通过m比特的模拟信号的第一模拟/数字转换，具有与第一满量程值相关联的m小于n的模拟信号，以及在与第二满量程相关联的m位上的模拟信号的第二模拟/数字转换全尺寸值比第一大2n-m倍。两个模拟/数字转换同时执行，分别传送m位的第一中间数字字和m位的第二中间数字字。该方法还包括在两个模拟/数字转换之后执行的数字后处理，并产生从扩展到n位的两个中间数字字中的至少一个开始的n位数字字，以及从至少一个阈值数字指示代表的至少一个阈值小于或等于第一满量程值。

5. 发明授权

US09071260B2 Method and related device for generating a digital output signal corresponding to an analog input signal 有权
标题翻译：用于产生对应于模拟输入信号的数字输出信号的方法和相关装置
公开(公告)号：US09071260B2
公开(公告)日：2015-06-30
申请号：US14447050
申请日：2014-07-30
申请人： STMicroelectronics S.r.l.
发明人： Mario Chiricosta , Calogero Marco Ippolito , Mario Maiore , Orlando Peluso , Michele Vaiana
IPC分类号： H03M1/20 , H03M1/06 , H03M1/12
CPC分类号： H03M1/0626 , H03M1/0639 , H03M1/12 , H03M1/20
摘要： An embodiment of a circuit includes an input node, a generator, a combiner, a converter, and a filter. The input node is configured to receive an input signal in a first domain, and the generator is configured to generate a periodic signal in the first domain. The combiner is configured to combine the input and periodic signals into a resulting signal in the first domain, and the converter is configured to convert the resulting signal into a converted signal in a second domain. And the filter is configured to remove from the converted signal substantially all of a frequency component of the converted signal having substantially a same frequency as a frequency component of the periodic signal.
摘要翻译：电路的实施例包括输入节点，发生器，组合器，转换器和滤波器。输入节点被配置为在第一域中接收输入信号，并且发生器被配置为在第一域中产生周期性信号。组合器被配置为将输入和周期信号组合成第一域中的结果信号，并且转换器被配置为将结果信号转换为第二域中的转换信号。并且滤波器被配置为从转换的信号中移除基本上所有的转换信号的频率分量具有与周期信号的频率分量基本相同的频率。

6. 发明申请

US20150138007A1 ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD 有权
标题翻译：模拟数字转换器和模拟数字转换方法
公开(公告)号：US20150138007A1
公开(公告)日：2015-05-21
申请号：US14548886
申请日：2014-11-20
申请人： Kabushiki Kaisha Toshiba
发明人： Kei SHIRAISHI , Junya MATSUNO , Masanori FURUTA
IPC分类号： H03M1/20 , H03M1/36 , H03M1/18 , H03M1/12
CPC分类号： H03M1/20 , H03M1/0695 , H03M1/1245 , H03M1/164 , H03M1/18 , H03M1/36 , H03M1/466 , H03M1/56 , H03M3/46
摘要： According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit.
摘要翻译：根据实施例，模数（AD）转换器包括第一AD转换单元，选择器和第二AD转换单元。第一AD转换单元在第一周期中执行模拟信号的AD转换，以产生高位数字信号。选择器基于高位数字信号选择不少于一个参考电压，以在比满量程更窄的电压范围内获得所选参考电压组。第二AD转换单元通过使用所选择的参考电压组来执行模拟信号的AD转换。第一时段在模拟信号稳定之前开始，直到对应于第一AD转换单元和第二AD转换单元的总分辨率的精度。

7. 发明申请

US20150129744A1 A/D CONVERTER, SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM 审中-公开
标题翻译： A / D转换器，固态图像传感器和成像系统
公开(公告)号：US20150129744A1
公开(公告)日：2015-05-14
申请号：US14520426
申请日：2014-10-22
申请人： Canon Kabushiki Kaisha
发明人： Kazuhiro Sonoda , Shintaro Takenaka
IPC分类号： H03M1/34 , H03K3/037 , H03K3/64
CPC分类号： H03K3/64 , H03M1/20 , H03M1/56
摘要： An A/D converter includes a comparator configured to compare an input voltage and a reference signal changing monotonically with respect to time and output a comparison result signal indicating a comparison result, a pulse signal generation circuit configured to generate a pulse signal in accordance with the comparison result signal, a counting unit configured to receive a first clock signal, and to count the first clock signal from a start of changing a level of the reference signal to when a level of the comparison result signal is changed, and a latch unit configured to latch the pulse signal at a timing which is defined by a plurality of clock signals including a second clock signal in phase with the first clock signal and a third clock signal having a different phase from that of the second clock signal.
摘要翻译： A / D转换器包括：比较器，被配置为比较输入电压和参考信号相对于时间单调变化，并输出表示比较结果的比较结果信号;脉冲信号产生电路，被配置为根据比较结果信号，被配置为接收第一时钟信号的计数单元，并且从开始将参考信号的电平改变到比较结果信号的电平改变时对第一时钟信号进行计数;以及闩锁单元配置以由包括与第一时钟信号同相的第二时钟信号的多个时钟信号定义的定时和与第二时钟信号具有不同相位的第三时钟信号的定时锁存脉冲信号。

8. 发明授权

US08981983B2 A/D conversion circuit, solid-state image sensor, and camera system 有权
标题翻译： A / D转换电路，固态图像传感器和相机系统
公开(公告)号：US08981983B2
公开(公告)日：2015-03-17
申请号：US13672252
申请日：2012-11-08
申请人： Sony Corporation
发明人： Yasuaki Hisamatsu
IPC分类号： H03M1/12 , H04N5/363 , H03K23/62 , H03M1/10 , H03M1/20 , H04N5/335 , H04N5/378 , H03M1/56
CPC分类号： H04N5/363 , H03K23/62 , H03M1/1023 , H03M1/12 , H03M1/123 , H03M1/1295 , H03M1/20 , H03M1/56 , H04N5/335 , H04N5/378
摘要： An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.
摘要翻译：可以在保持上/下计数值的同时切换计数器能够在时钟的两个边缘进行计数的A / D转换电路，并且计数操作的占空比即使使用双边计数，固态图像传感器和照相机系统也难以扭曲。

9. 发明授权

US08779961B2 Scalable successive-approximation-register analog-to-digital converter 有权
标题翻译：可扩展的逐次逼近寄存器模数转换器
公开(公告)号：US08779961B2
公开(公告)日：2014-07-15
申请号：US13666251
申请日：2012-11-01
申请人： Marvell International Ltd.
发明人： Sehat Sutardja , Giovanni Antonio Cesura , Francesco Rezzi , Rinaldo Castello
IPC分类号： H03M1/20 , H03M1/12 , H03M1/00
CPC分类号： H03M1/20 , A01K79/00 , A23K50/80 , H03M1/002 , H03M1/0643 , H03M1/0678 , H03M1/1076 , H03M1/121 , H03M1/468
摘要： A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.
摘要翻译：一种包括被配置为产生时钟的时钟发生器的系统; 多个模数转换器，每个被配置为基于时钟转换信号，并且响应于基于时钟转换信号来输出第一位数; 以及平均模块，被配置为从所述多个模数转换器中的每一个接收所述第一数量的位，并输出第二数量的位。第二位数大于第一位数。

10. 发明授权

US08773307B2 Wide null Forming system with beamforming 有权
标题翻译：宽零波束成形系统
公开(公告)号：US08773307B2
公开(公告)日：2014-07-08
申请号：US12952029
申请日：2010-11-22
申请人： Donald C. D. Chang , Yulan Sun , Yuanchang Liu
发明人： Donald C. D. Chang , Yulan Sun , Yuanchang Liu
IPC分类号： G01S3/16 , H01Q3/00
CPC分类号： H03M1/002 , H03M1/0641 , H03M1/08 , H03M1/12 , H03M1/1205 , H03M1/1215 , H03M1/188 , H03M1/20 , H04B1/0475 , H04B1/123 , H04B7/10 , H04L27/06
摘要： A novel wide null forming system achieves both wide bandwidth and beam width null through employing an antenna array to receive and transmit signals to which a complex null weight vector, calculated by perturbation program, is applied. The novel wide null forming system includes a multiple-element antenna array for receiving or transmitting signals. Multiple conditioning units matching the number of elements is present to condition the signals for proper reception and analysis, after which a series of complex multiplier processors adds complex weights. After being weighted each constituent beam is combined in an adding processor to form one composite beam for use by the user.
摘要翻译：通过采用天线阵列来接收和发送通过扰动程序计算的复零零权重向量的信号，新的宽零空位形成系统实现宽带宽和波束宽度零。新的宽零位成形系统包括用于接收或发送信号的多元件天线阵列。存在与元件数量相匹配的多个调节单元来调节信号以进行适当的接收和分析，之后一系列复杂乘法器处理器增加了复杂的权重。在加权之后，每个组成光束在加法处理器中组合以形成用户使用的一个组合光束。

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