专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140082451A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC 审中-公开
标题翻译：有效和可扩展的循环冗余使用GALOIS-FIELD ARTIMETIC检查电路
公开(公告)号：US20140082451A1
公开(公告)日：2014-03-20
申请号：US14083059
申请日：2013-11-18
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
摘要翻译：本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

2. 发明授权

US08154432B2 Digital to analog converter (DAC) having high dynamic range 有权
标题翻译：具有高动态范围的数模转换器（DAC）
公开(公告)号：US08154432B2
公开(公告)日：2012-04-10
申请号：US12728749
申请日：2010-03-22
申请人： Valery S. Kaper , John P. Bettencourt
发明人： Valery S. Kaper , John P. Bettencourt
IPC分类号： H03M1/10
CPC分类号： H03M1/1052 , H03M1/66
摘要： A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.
摘要翻译：一种具有：数字预失真电路的数字预失真电路，由数字信号馈送以扭曲数字信号; 耦合到所述校准电路的输出的数模转换器（DAC）核心部分，用于将失真的数字信号转换成对应的模拟信号，所述DAC核部分根据馈送到所述DAC核心部分的控制信号执行转换; 功率放大器（PA）部分，耦合到DAC核心部分的输出端，用于放大模拟信号的功率; 以及耦合到所述功率放大器的输出的校准电路，用于响应于功率放大模拟信号中的功率而产生用于DAC核心部分的控制信号。

3. 发明申请

US20110227770A1 DIGITAL-TO-ANALOG CONVERTER (DAC) 有权
标题翻译：数模转换器（DAC）
公开(公告)号：US20110227770A1
公开(公告)日：2011-09-22
申请号：US12728749
申请日：2010-03-22
申请人： Valery S. Kaper , John P. Bettencourt
发明人： Valery S. Kaper , John P. Bettencourt
IPC分类号： H03M1/66 , H03M1/10
CPC分类号： H03M1/1052 , H03M1/66
摘要： A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.
摘要翻译：一种具有：数字预失真电路的数字预失真电路，由数字信号馈送以扭曲数字信号; 耦合到所述校准电路的输出的数模转换器（DAC）核心部分，用于将失真的数字信号转换成对应的模拟信号，所述DAC核部分根据馈送到所述DAC核心部分的控制信号执行转换; 功率放大器（PA）部分，耦合到DAC核心部分的输出端，用于放大模拟信号的功率; 以及耦合到所述功率放大器的输出的校准电路，用于响应于功率放大模拟信号中的功率而产生用于DAC核心部分的控制信号。

4. 发明申请

US20100314560A1 D/A Converter and electron beam exposure apparatus 有权
标题翻译： D / A转换器和电子束曝光装置
公开(公告)号：US20100314560A1
公开(公告)日：2010-12-16
申请号：US12800568
申请日：2010-05-18
申请人： Hidefumi Yabara
发明人： Hidefumi Yabara
IPC分类号： G21K5/00 , H03M1/06
CPC分类号： H03M1/1052 , H03M1/687
摘要： A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code to be set to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing the error detection processing section to generate the digital code to be set to the correction D/A converter unit when judging that the value of the one bit current source changes.
摘要翻译： AD / A转换器包括具有执行高阶比特D / A转换的第一D / A转换器单元的D / A转换器基座部分和执行低位比特的D / A转换的第二D / A转换器单元，并且包括辅助比特分配与最低有效位相同的权重，校正D / A转换器部分，产生将被设置到校正D / A转换器部分中的校正D / A转换器单元的数字代码的错误检测处理部分，以及控制部分。控制部分将一位电流源与另一位电流源以比一位电流源更低的顺序进行比较，并通过使错误检测处理部分生成要设置为的数字代码来校正一位电流源的值校正D / A转换器单元当判断一位电流源的值改变时。

5. 发明授权

US07425908B2 Method of generating a digital signal that is representative of match errors in an analog digital conversion system with the time interleaving, and an analog digital converter with time interleaving using same 失效
标题翻译：在具有时间交织的模拟数字转换系统中生成代表匹配误差的数字信号的方法，以及具有使用其的时间交织的模拟数字转换器
公开(公告)号：US07425908B2
公开(公告)日：2008-09-16
申请号：US10581549
申请日：2004-11-30
申请人： Patrick Gremillet
发明人： Patrick Gremillet
IPC分类号： H03M1/10
CPC分类号： H03M1/1052 , H03M1/1085 , H03M1/1215
摘要： A method for generating a digital signal representative of the pairing error between the channels of an analog digital conversion system with time interleaving, and a method for suppressing the errors thus calculated and an analog digital conversion system with time interleaving using same. The method comprises determining a spectrum (11-12) of the digital signal as a function of a frequency response of the analog digital conversion system with time interleaving (CAN 10) to at least one analog calibration signal (IC), and generating a “comb” signal whose spectrum is composed of frequency lines kFs/N, where Fs is a sampling frequency and N a number of channels of the analog digital conversion system with time interleaving, and whose amplitude is dependent on the frequency response of the analog digital converter.
摘要翻译：一种用于产生代表模拟数字转换系统的信道与时间交织之间的配对误差的数字信号的方法以及用于抑制如此计算的误差的方法和使用其的时间交织的模拟数字转换系统。该方法包括根据随时间交织（CAN 10）至少一个模拟校准信号（IC）的模拟数字转换系统的频率响应来确定数字信号的频谱（11-12），并产生“ 梳状“信号，其频谱由频率线kFs / N组成，其中Fs是采样频率，N是具有时间交织的模拟数字转换系统的通道数，并且其幅度取决于模拟数字转换器的频率响应。

6. 发明授权

US06720896B2 Analog/digital or digital/analog converter having internal reference voltage selection 有权
标题翻译：具有内部参考电压选择的模拟/数字或数字/模拟转换器
公开(公告)号：US06720896B2
公开(公告)日：2004-04-13
申请号：US10067173
申请日：2002-02-04
申请人： Joseph Semmler , Frank Lehmacher
发明人： Joseph Semmler , Frank Lehmacher
IPC分类号： H03M110
CPC分类号： H03M1/1052 , H03M1/0619 , H03M1/1023 , H03M1/468 , H03M1/804
摘要： An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which selects a voltage based on a selection signal and feeds the reference voltage to a conversion device of the converter. A correction network is provided for correcting offset and linearity errors. The plurality of reference voltages are freely selectable reference voltages, and the specific reference voltage defining the conversion is freely selectable, that is, it is freely selectable what reference voltage is used to carry out a respective conversion.
摘要翻译： A / D转换器或D / A转换器具有内部电压选择装置。多个参考电压可供选择装置选择，选择装置根据选择信号选择电压，并将参考电压馈送到转换器的转换装置。提供校正网络用于校正偏移和线性误差。多个参考电压是可自由选择的参考电压，并且限定转换的特定参考电压是可自由选择的，即，可以自由地选择使用什么参考电压来执行相应的转换。

7. 发明申请

US20020126033A1 Analog/digital or digital/analog converter 有权
标题翻译：模拟/数字或数字/模拟转换器
公开(公告)号：US20020126033A1
公开(公告)日：2002-09-12
申请号：US10067173
申请日：2002-02-04
发明人： Joseph Semmler , Frank Lehmacher
IPC分类号： H03M001/34
CPC分类号： H03M1/1052 , H03M1/0619 , H03M1/1023 , H03M1/468 , H03M1/804
摘要： An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which selects a voltage based on a selection signal and feeds the reference voltage to a conversion device of the converter. A correction network is provided for correcting offset and linearity errors. The plurality of reference voltages are freely selectable reference voltages, and the specific reference voltage defining the conversion is freely selectable, that is, it is freely selectable what reference voltage is used to carry out a respective conversion.
摘要翻译： A / D转换器或D / A转换器具有内部电压选择装置。多个参考电压可供选择装置选择，选择装置根据选择信号选择电压，并将参考电压馈送到转换器的转换装置。提供校正网络用于校正偏移和线性误差。多个参考电压是可自由选择的参考电压，并且限定转换的特定参考电压是可自由选择的，即，可以自由地选择使用什么参考电压来执行相应的转换。

8. 发明申请

US20160291056A1 BAND OVERLAY SEPARATOR 有权
标题翻译：带覆盖分隔器
公开(公告)号：US20160291056A1
公开(公告)日：2016-10-06
申请号：US14674344
申请日：2015-03-31
申请人： Tektronix, Inc.
发明人： John J. Pickerd , Kan Tan
IPC分类号： G01R13/02 , G01R13/22
CPC分类号： G01R13/0218 , G01R13/0272 , G01R13/225 , H03M1/1052 , H03M1/1215
摘要： A test and measurement instrument including a splitter configured to split an input signal into at least two split signals, at least two harmonic mixers configured to mix an associated split signal with an associated harmonic signal to generate an associated mixed signal, at least two digitizers configured to digitize the associated mixed signal, at least two MIMO polyphase filter arrays configured to filter the associated digitized mixed signal of an associated digitizer of the at least two digitizers, at least two pairs of band separation filters configured to receive the associated digitized mixed signals from each of the MIMO polyphase filter arrays and output a low band of the input signal and a high band of the input signal based on a time different between the at least two digitizers and a phase drift of a local oscillator, and a combiner configured to combine the low band of the input signal and the high band of the input signal to form a reconstructed input signal.
摘要翻译：一种包括分配器的测试和测量仪器，其被配置为将输入信号分成至少两个分离信号，至少两个谐波混合器被配置为将相关联的分离信号与相关联的谐波信号混合以产生相关联的混合信号，至少两个数字化器被配置至少两个MIMO多相滤波器阵列被配置为对所述至少两个数字化仪的相关联的数字转换器的相关联的数字化混合信号进行数字化，至少两对频带分离滤波器被配置成从相关联的数字化混合信号中接收相关联的数字化混合信号每个MIMO多相滤波器阵列，并且基于所述至少两个数字转换器之间的时间和本地振荡器的相位漂移而输出所述输入信号的低频带和所述输入信号的高频带，以及被配置为组合的组合器输入信号的低频带和输入信号的高频带，以形成重构的输入信号。

9. 发明授权

US09281834B1 N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration 有权
标题翻译：具有偏移增益和定时不匹配校准的N路径交错模数转换器（ADC）
公开(公告)号：US09281834B1
公开(公告)日：2016-03-08
申请号：US14927077
申请日：2015-10-29
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1023 , H03M1/0626 , H03M1/0836 , H03M1/1052 , H03M1/121 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.
摘要翻译：提供了一种用于校准n路时间交错模数转换器（ADC）中的定时失配的系统和方法。该方法将模拟信号与n路交错ADC进行数字化，产生交错的ADC信号。在第一过程中，交错的ADC信号的相位旋转90度，产生旋转的信号。该旋转可以使用具有{0.5,0，-0.5}的抽头的有限脉冲响应（FIR）滤波器，作为导数滤波器使能，或作为希尔伯特变换来完成。在并行的第二过程中，交织的ADC信号被延迟，产生延迟的信号。旋转的信号乘以延迟信号以产生定时误差信号。使用定时误差信号，对ADC信号路径累积定时误差，并且施加使n个ADC信号路径中的每一个中的定时误差最小化的校正。

10. 发明授权

US09160310B2 Linearity compensator for removing nonlinear distortion 有权
标题翻译：用于去除非线性失真的线性补偿器
公开(公告)号：US09160310B2
公开(公告)日：2015-10-13
申请号：US13915484
申请日：2013-06-11
申请人： Scott R. Velazquez , Richard J. Velazquez
发明人： Scott R. Velazquez , Richard J. Velazquez
IPC分类号： H03H21/00 , H04L27/26 , H04B1/00 , H04L25/02 , H04L25/14 , H04L27/00
CPC分类号： H03H21/0067 , H03H21/0043 , H03M1/1052 , H04B1/001 , H04L25/02 , H04L25/14 , H04L27/0006 , H04L27/0012 , H04L27/265
摘要： The present invention is an improved linearizer that implements more complex transfer functions to provide the necessary linearization performance with a reasonable amount of signal processing resources. Particularly, the linearizer operates on an analog-to-digital converter and comprises a distortion compensator and one or more factored Volterra compensators, which may include a second-order factored Volterra compensator, a third-order factored Volterra compensator, and additional higher-order factored Volterra compensators. Inclusion of factored Volterra distortion compensators improves linearization processing performance while significantly reducing the computational complexity compared to a traditional Volterra-based compensator.
摘要翻译：本发明是一种改进的线性化器，其实现更复杂的传递函数，以提供具有合理数量的信号处理资源的必要的线性化性能。特别地，线性化器在模数转换器上操作，并且包括失真补偿器和一个或多个因子Volterra补偿器，其可以包括二阶因子Volterra补偿器，三阶因子Volterra补偿器和附加高阶沃尔特拉补偿器。与传统的基于沃尔泰拉的补偿器相比，包含因子Volterra失真补偿器提高了线性化处理性能，同时显着降低了计算复杂度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式