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1. 发明授权

US08966291B2 Method and apparatus for reducing dynamic power within system-on-a-chip routing resources 有权
标题翻译：降低片上系统路由资源中的动态功率的方法和装置
公开(公告)号：US08966291B2
公开(公告)日：2015-02-24
申请号：US12977553
申请日：2010-12-23
申请人： Jaya Prakash Subramaniam Ganasan , Martyn Ryan Shirlen
发明人： Jaya Prakash Subramaniam Ganasan , Martyn Ryan Shirlen
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus.
摘要翻译：一种在总线上传输数据的方法。通过了解总线的功率特性和通过总线传输的数据的特性，可以以这样的方式对数据进行编码，以便通过跨总线以未编码格式发送相同数据节省系统功率。可以在通过总线传输数据之前选择编码方法，并且可以根据要通过总线传输的数据而改变。

2. 发明申请

US20130117593A1 Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects 审中-公开
标题翻译：总线互连功率降低的低延迟时钟门控方案
公开(公告)号：US20130117593A1
公开(公告)日：2013-05-09
申请号：US13290250
申请日：2011-11-07
申请人： Prudhvi N. Nooney , Jaya Prakash Subramaniam Ganasan , Joseph L. Van Swearingen , Richard Gerard Hofmann
发明人： Prudhvi N. Nooney , Jaya Prakash Subramaniam Ganasan , Joseph L. Van Swearingen , Richard Gerard Hofmann
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151 , Y02D50/20
摘要： A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle.
摘要翻译：一种片上系统（SoC），包括控制器，活动计数器，参考模式检测逻辑，主模式检测逻辑，仲裁器，比较器，跟踪器电路，延迟单元电路和请求掩码电路耦合到总线。总线配置为支持主控制。控制器被配置为使组件进入低功率状态。活动计数器配置为监视活动。检测逻辑被配置为在基于活动的时钟上操作或者始终处于时钟上。仲裁器被配置为选择启动器。比较器配置为比较检测逻辑的输出。跟踪器电路被配置为跟踪组件的选择。延迟单元电路被配置为存储组件的输出。请求屏蔽电路被配置为防止对仲裁器的请求或从先前时钟周期进行的任何仲裁器选择的请求。

3. 发明授权

US07174403B2 Plural bus arbitrations per cycle via higher-frequency arbiter 有权
标题翻译：通过高频仲裁器，每个周期进行多次总线仲裁
公开(公告)号：US07174403B2
公开(公告)日：2007-02-06
申请号：US11066507
申请日：2005-02-24
申请人： Jaya Prakash Subramaniam Ganasan
发明人： Jaya Prakash Subramaniam Ganasan
IPC分类号： G06F13/14 , G06F13/36 , G06F1/10
CPC分类号： G06F13/4022 , H04L49/101 , Y02D10/14 , Y02D10/151
摘要： An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.
摘要翻译：总线系统中的仲裁器通过以大于总线频率的频率工作，在单个总线频率时钟周期内仲裁多个总线事务请求。这允许在单个总线频率时钟周期中进行两个或多个仲裁操作，其中一个仲裁逻辑实例。仲裁器可以对两个或多个从设备进行仲裁，或者仲裁指向同一从设备的多个主设备请求。仲裁器频率可以是可变的，并且可以基于例如先前的总线活动来预测。如果只有一个总线事务请求正在等待，则仲裁器频率可以等于总线频率。较早的仲裁决定的结果可以用于在相同的总线频率时钟周期中更智能地进行后续的仲裁决策。

4. 发明授权

US06857029B2 Scalable on-chip bus performance monitoring synchronization mechanism and method of use 有权
标题翻译：可扩展的片上总线性能监控同步机制和使用方法
公开(公告)号：US06857029B2
公开(公告)日：2005-02-15
申请号：US10137084
申请日：2002-04-30
申请人： Jaya Prakash Subramaniam Ganasan , Adger Erik Harvin, III , Richard Gerard Hofmann , Perry Willmann Remaklus, Jr.
发明人： Jaya Prakash Subramaniam Ganasan , Adger Erik Harvin, III , Richard Gerard Hofmann , Perry Willmann Remaklus, Jr.
IPC分类号： G06F1/12 , G06F13/00
CPC分类号： G06F1/12
摘要： A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave devices, a plurality of generic signals and a plurality of control signals. The monitoring mechanism includes a plurality of control registers coupled to the muxing logic to allow for the selection of master, slave, generic and pipeline stage events to be counted. Finally, the monitoring mechanism includes synchronizing logic coupled to the plurality of registers for providing and receiving synchronizing signals to and from the monitors coupled thereto to allow for scalability. The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a “lego-like” fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique. For these designs where multiple monitor instances may be required, this enhances wireability by allowing the SOC designer to scatter the monitor instance locations virtually anywhere within the smaller areas of unused chip space, and simply wire the synchronization signals among the monitor instances to allow for synchronous operation.
摘要翻译：公开了一种用于芯片系统（SOC）的总线性能监视机制。该系统包括适于耦合到多个主设备，多个从设备，多个通用信号和多个控制信号的多路复用逻辑。监视机制包括耦合到多路复用逻辑的多个控制寄存器，以允许对主，从，通用和流水线级事件的选择进行计数。最后，监视机制包括与多个寄存器耦合的同步逻辑，用于提供和接收与耦合到其的监视器同步信号以允许可扩展性。根据本发明的可扩展的片上总线性能监视系统在SOC实现中执行片上总线监视，同时消除如上所述的陷阱。通过简约的设计方法，可以通过在SOC设计中使用这些监视机制的多个监视器实例，同时保持它们之间的同步来实现可扩展性。如果SOC设计的大小增加，则通过简单地添加附加的监视器实例来实现可扩展性。然后，多个监视器实例可以以“lego-like”的方式连接，允许每个监视器实例通过可伸缩的同步技术独立地或彼此并行操作。对于可能需要多个监视器实例的这些设计，通过允许SOC设计人员将监视器实例位置实际上分散在未使用的芯片空间的较小区域内的任何位置，从而提高了可线性，并且简单地将监视器实例之间的同步信号连接起来以允许同步操作。

5. 发明授权

US09286257B2 Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods 有权
标题翻译：总线互连及相关设备，系统和方法的总线时钟频率缩放
公开(公告)号：US09286257B2
公开(公告)日：2016-03-15
申请号：US13015657
申请日：2011-01-28
申请人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan , Brandon Wayne Lewis
发明人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan , Brandon Wayne Lewis
IPC分类号： G06F13/00 , G06F13/40 , G06F1/06 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译：公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。总线互连时钟信号对互连网络进行时钟。控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。

6. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

7. 发明申请

US20100005208A1 Efficient Execution of Memory Barrier Bus Commands 有权
标题翻译：高效执行内存障碍总线命令
公开(公告)号：US20100005208A1
公开(公告)日：2010-01-07
申请号：US12561381
申请日：2009-09-17
申请人： James Edward Sullivan, JR. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, JR. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

8. 发明授权

US06973520B2 System and method for providing improved bus utilization via target directed completion 失效
标题翻译：通过目标定向完成提供改进的总线利用率的系统和方法
公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译：公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。该机制为进行成功的数据传输提供了额外的总线带宽。

9. 发明授权

US07921249B2 Weakly ordered processing systems and methods 有权
标题翻译：处理系统和方法薄弱
公开(公告)号：US07921249B2
公开(公告)日：2011-04-05
申请号：US12561381
申请日：2009-09-17
申请人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

10. 发明授权

US07917676B2 Efficient execution of memory barrier bus commands with order constrained memory accesses 有权
标题翻译：具有订单约束的存储器访问的存储器障碍总线命令的高效执行
公开(公告)号：US07917676B2
公开(公告)日：2011-03-29
申请号：US11397287
申请日：2006-04-04
申请人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

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