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1. 发明授权

US08612690B2 Method for filtering traffic to a physically-tagged data cache 有权
标题翻译：将流量过滤到物理标记的数据高速缓存的方法
公开(公告)号：US08612690B2
公开(公告)日：2013-12-17
申请号：US13426647
申请日：2012-03-22
申请人： Robert D. Clancy , James Norris Dieffenderfer , Thomas Philip Speier
发明人： Robert D. Clancy , James Norris Dieffenderfer , Thomas Philip Speier
IPC分类号： G06F12/10 , G06F7/04
CPC分类号： G06F12/1054 , G06F12/0864 , G06F12/1045 , G06F12/1063 , Y02D10/13
摘要： Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a data array that stores data elements, a physically-tagged tag array, and a virtually-tagged tag array. In one embodiment, the virtually-tagged tag array receives a virtual address. If there is a match for the virtual address in the virtually-tagged tag array, the virtually-tagged tag array outputs, to the data array, a way stored in the virtually-tagged tag array for the virtual address. In addition, in one embodiment, the virtually-tagged tag array disables the physically-tagged tag array. Using the way output by the virtually-tagged tag array, a desired data element in the data array is addressed.
摘要翻译：公开了数据高速缓存的实施例，其提供了对数据高速缓存的物理标记的标签阵列的访问的数量的大量减少。通常，数据高速缓存包括存储数据元素，物理标记的标签阵列和虚拟标记的标签阵列的数据阵列。在一个实施例中，虚拟标记的标签阵列接收虚拟地址。如果虚拟标记的标签阵列中的虚拟地址匹配，则虚拟标记的标签阵列将数据阵列中的虚拟地址标记在虚拟标记的数组中。此外，在一个实施例中，虚拟标记的标签阵列禁用物理标记的标签阵列。使用由虚拟标记的标签数组输出的方式，寻址数据数组中所需的数据元素。

2. 发明申请

US20130191559A1 PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE DATA FILL BUFFERS 审中-公开
标题翻译：防止参考数据填充缓冲区的高速局部性的偏移
公开(公告)号：US20130191559A1
公开(公告)日：2013-07-25
申请号：US13451010
申请日：2012-04-19
申请人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
发明人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
IPC分类号： G06F3/00
CPC分类号： G06F12/0859 , G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
摘要翻译：本公开涉及以高参考时间局部性访问存储器内容。本公开的实施例将内容存储在数据缓冲器中，确定数据缓冲器的内容具有高的参考时间局部性，并且针对针对内容的每个操作而不是存储内容的高速缓存来访问数据缓冲器。

3. 发明申请

US20130151799A1 Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions 有权
标题翻译：在多个内存区域自动排序强顺序，设备和独占交易
公开(公告)号：US20130151799A1
公开(公告)日：2013-06-13
申请号：US13315370
申请日：2011-12-09
申请人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
发明人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
IPC分类号： G06F12/00
CPC分类号： G06F13/1621
摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
摘要翻译：描述了用于控制弱订单存储系统中有序访问的高效技术。存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。对于保证完成的每个存储器请求，存储器访问计数器递减。与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

4. 发明申请

US20120059995A1 Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy 有权
标题翻译：在多级缓存层次结构中减少铸件的装置和方法
公开(公告)号：US20120059995A1
公开(公告)日：2012-03-08
申请号：US13292651
申请日：2011-11-09
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译：技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。防止所选线路的分配节省与分配相关联的功率。

5. 发明授权

US06961276B2 Random access memory having an adaptable latency 失效
公开(公告)号：US06961276B2
公开(公告)日：2005-11-01
申请号：US10664789
申请日：2003-09-17
申请人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
发明人： Francois Ibrahim Atallah , James Norris Dieffenderfer , Jeffrey H. Fischer , Michael Thomas Fragano , Daniel Stephen Geise , Jeffery Howard Oppold , Michael R. Ouellette , Neelesh Govindaraya Pai , William Robert Reohr , Joel Abraham Silberman , Thomas Philip Speier
IPC分类号： G11C7/02 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/22
CPC分类号： G11C7/22 , G11C7/06 , G11C7/1045
摘要： A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

6. 发明授权

US06816962B2 Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions 失效
标题翻译：将非法OP代码重新编码为单个非法OP代码以适应与预解码指令相关联的额外位
公开(公告)号：US06816962B2
公开(公告)日：2004-11-09
申请号：US10082085
申请日：2002-02-25
申请人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
发明人： Victor Roberts Augsburg , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Thomas Philip Speier
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/3017 , G06F9/30181
摘要： A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.
摘要翻译：一种用于利用非法操作码集合中的比特的方法和系统，以便能够将预解码的指令存储在指令高速缓存中，而不增加表示预解码指令所需的比特数。在从存储器获取指令时，检查操作码是否存在非法操作码集合中的成员资格。如果指令操作代码是该集合的成员，则该指令可能被重新编码以使用不同的，常见的非法操作码。如果指令操作码不是非法操作码集合的成员，而是以预解码格式代替存储在指令高速缓存中的指令，附加的预解码信息可以被存储在指令编码中利用由非法操作代码的重新编码已经腾出的操作代码空间的部分。

7. 发明授权

US10114750B2 Preventing the displacement of high temporal locality of reference data fill buffers 有权
公开(公告)号：US10114750B2
公开(公告)日：2018-10-30
申请号：US13451010
申请日：2012-04-19
申请人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
发明人： Robert D. Clancy , Thomas Philip Speier , James Norris Dieffenderfer
IPC分类号： G06F3/06 , G06F12/0855 , G06F12/0882
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

8. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

9. 发明授权

US08078803B2 Apparatus and methods to reduce castouts in a multi-level cache hierarchy 有权
标题翻译：减少多级缓存层次结构中的丢弃的装置和方法
公开(公告)号：US08078803B2
公开(公告)日：2011-12-13
申请号：US11669245
申请日：2007-01-31
申请人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Thomas Philip Speier , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译：技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。

10. 发明授权

US07353319B2 Method and apparatus for segregating shared and non-shared data in cache memory banks 有权
标题翻译：用于在高速缓存存储体中隔离共享和非共享数据的方法和装置
公开(公告)号：US07353319B2
公开(公告)日：2008-04-01
申请号：US11144207
申请日：2005-06-02
申请人： Thomas Philip Speier , James Norris Dieffenderfer
发明人： Thomas Philip Speier , James Norris Dieffenderfer
IPC分类号： G06F12/06
CPC分类号： G06F12/0848 , G06F12/0831 , G06F12/0837 , Y02D10/13
摘要： In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated for holding non-shared data. A non-shared data bank may be designated exclusively for holding non-shared data, so that shared data accesses do not interfere with non-shared accesses to that bank. Also, a shared data bank may be designated exclusively for holding shared data, and one or more banks may be designated for holding both shared and non-shared data. An access control circuit directs shared and non-shared accesses to respective banks based on receiving a shared indication signal in association with the accesses. Further, in one or more embodiments, the access control circuit reconfigures one or more bank designations responsive to a bank configuration signal.
摘要翻译：在多处理器系统中，控制对给定处理器的存储高速缓存的访问，使得共享数据访问被定向到指定用于保存共享数据的一个或多个库和/或非共享数据访问被定向到指定用于保存非共享数据的一个或多个库共享数据。非共享数据库可以专门用于保存非共享数据，使得共享数据访问不会干扰对该银行的非共享访问。此外，共享数据库可以被专门用于保存共享数据，并且可以指定一个或多个存储体来保存共享和非共享数据。访问控制电路基于接收与访问相关联的共享指示信号，将共享和非共享访问指向各个存储体。此外，在一个或多个实施例中，访问控制电路响应于存储体配置信号重新配置一个或多个存储体指定。

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