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1. 发明授权

US07518535B1 Generating a Gray code sequence for any even length using an intermediate binary sequence 失效
标题翻译：使用中间二进制序列生成任何均匀长度的格雷码序列
公开(公告)号：US07518535B1
公开(公告)日：2009-04-14
申请号：US11954451
申请日：2007-12-12
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2−L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2−L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.
摘要翻译：为具有L个成员的循环序列生成用于非标准序列长度的灰色序列。对于具有小于L / 2的数值（C / 2-L）的循环序列的二进制成员，最高有效位被强制为逻辑“1”以创建中间二进制成员。对于大于或等于数量（C / 2-L）的成员添加到二进制文件中以创建中间二进制文件。然后将中间二进制变换为具有非标准序列长度L的格雷码序列。

2. 发明授权

US07870448B2 In system diagnostics through scan matrix 失效
标题翻译：通过扫描矩阵进行系统诊断
公开(公告)号：US07870448B2
公开(公告)日：2011-01-11
申请号：US11958468
申请日：2007-12-18
申请人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
发明人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G06F11/267 , G01R31/318555
摘要： A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.
摘要翻译：公开了一种通过扫描矩阵进行系统诊断的方法，以及执行诊断的集成电路芯片。所述集成电路芯片可操作在多个边界扫描测试模式中，其中所述集成电路芯片中的至少一部分电路被测试，所述集成电路芯片包括扫描矩阵控制器和指令寄存器。提供扫描矩阵控制器用于将所述电路划分成多个矩阵，每个矩阵具有多个扫描元件。提供指令寄存器用于保持扫描矩阵控制器的指令，用于将芯片划分为所述多个矩阵。扫描矩阵控制器还被布置为通过将测试信号施加到电路的测试部分来根据指令寄存器中的指令来测试每个所述矩阵。

3. 发明授权

US07853738B2 Efficient load/store buffer memory management in a computer communications network data transmission switch 有权
标题翻译：有效的加载/存储缓冲存储器管理在计算机通信网络数据传输交换机中
公开(公告)号：US07853738B2
公开(公告)日：2010-12-14
申请号：US12191364
申请日：2008-08-14
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F13/385
摘要： A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).
摘要翻译：公开了一种用于观察连接到计算机通信网络数据传输交换机的外围设备中的数据移动模式的技术，以便（统计）确定外围设备是否被用作“负载密集型”设备或作为“商店密集型”设备（或既不是类型）在规定的时间段内。该设置用于动态调整（并重新分配）分配给连接到外围设备的交换机传输端口的“出站”和“入站”缓冲存储器大小，在该设备以“负载密集型”或 “店铺密集”模式。本发明适用于所有类型的通信网络交换机（即“桥接”，“集线器”，“路由器”等）。

4. 发明申请

US20090158225A1 METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY 有权
标题翻译：用于在设计层次上自动访问内部信号或端口的方法和系统
公开(公告)号：US20090158225A1
公开(公告)日：2009-06-18
申请号：US11955689
申请日：2007-12-13
申请人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
发明人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.
摘要翻译：公开了一种采用分层路径数据库生成器来访问集成电路设计的设计层级中的内部信号或端口名称的方法。该方法包括将设计文件输入到分层路径数据库生成器中的步骤; 并且所述分级路径数据库生成器确定所述设计文件中的端口和信号，并且以逻辑层级顺序将所述端口和信号的名称存储在分层数据库中。该方法还包括提供测试用例以验证集成电路设计的定义方面的步骤; 解析测试用例以识别其中的所有信号和端口名称; 并且对于在测试用例中识别的每个信号和端口名称，将所述每个名称输入到分层路径数据库生成器中，并从该生成器获得与所述每个信号和端口名称相关联的分层路径。

5. 发明申请

US20090158105A1 IN SYSTEM DIAGNOSTICS THROUGH SCAN MATRIX 失效
标题翻译：通过扫描矩阵进行系统诊断
公开(公告)号：US20090158105A1
公开(公告)日：2009-06-18
申请号：US11958468
申请日：2007-12-18
申请人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
发明人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
IPC分类号： G01R31/3185 , G06F11/26
CPC分类号： G06F11/267 , G01R31/318555
摘要： A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.
摘要翻译：公开了一种通过扫描矩阵进行系统诊断的方法，以及执行诊断的集成电路芯片。所述集成电路芯片可操作在多个边界扫描测试模式中，其中所述集成电路芯片中的至少一部分电路被测试，所述集成电路芯片包括扫描矩阵控制器和指令寄存器。提供扫描矩阵控制器用于将所述电路划分成多个矩阵，每个矩阵具有多个扫描元件。提供指令寄存器用于保持扫描矩阵控制器的指令，用于将芯片划分为所述多个矩阵。扫描矩阵控制器还被布置为通过将测试信号施加到电路的测试部分来根据指令寄存器中的指令来测试每个所述矩阵。

6. 发明授权

US08001503B2 Method and system for automatically accessing internal signals or ports in a design hierarchy 有权
标题翻译：自动访问设计层级结构内部信号或端口的方法和系统
公开(公告)号：US08001503B2
公开(公告)日：2011-08-16
申请号：US11955689
申请日：2007-12-13
申请人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
发明人： Jayashri Arsikere Basappa , Sandeep Niranjan Tippannanavar , Venkatasreekanth Prudvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.
摘要翻译：公开了一种采用分层路径数据库生成器来访问集成电路设计的设计层级中的内部信号或端口名称的方法。该方法包括将设计文件输入到分层路径数据库生成器中的步骤; 并且所述分级路径数据库生成器确定所述设计文件中的端口和信号，并且以逻辑层级顺序将所述端口和信号的名称存储在分层数据库中。该方法还包括提供测试用例以验证集成电路设计的定义方面的步骤; 解析测试用例以识别其中的所有信号和端口名称; 并且对于在测试用例中识别的每个信号和端口名称，将所述每个名称输入到分层路径数据库生成器中，并从该生成器获得与所述每个信号和端口名称相关联的分层路径。

7. 发明授权

US07667629B2 Generating a gray code for an odd length sequence using a virtual space 失效
标题翻译：使用虚拟空间生成奇数长度序列的灰色代码
公开(公告)号：US07667629B2
公开(公告)日：2010-02-23
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

8. 发明申请

US20100042762A1 Efficient Load/Store Buffer Memory Management in a Computer Communications Network Data Transmission Switch 有权
标题翻译：在计算机通信网络数据传输交换机中高效加载/存储缓冲存储器管理
公开(公告)号：US20100042762A1
公开(公告)日：2010-02-18
申请号：US12191364
申请日：2008-08-14
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).
摘要翻译：公开了一种用于观察连接到计算机通信网络数据传输交换机的外围设备中的数据移动模式的技术，以便（统计）确定外围设备是否被用作“负载密集型”设备或作为“商店密集型”设备（或既不是类型）在规定的时间段内。该设置用于动态调整（并重新分配）分配给连接到外围设备的交换机传输端口的“出站”和“入站”缓冲存储器大小，在该设备以“负载密集型”或 “店铺密集”模式。本发明适用于所有类型的通信网络交换机（即“桥接”，“集线器”，“路由器”等）。

9. 发明申请

US20090295608A1 GENERATING A GRAY CODE FOR AN ODD LENGTH SEQUENCE USING A VIRTUAL SPACE 失效
标题翻译：使用虚拟空间生成ODD长度序列的灰度代码
公开(公告)号：US20090295608A1
公开(公告)日：2009-12-03
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

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