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1. 发明申请

US20100134332A1 ENCODING A GRAY CODE SEQUENCE FOR AN ODD LENGTH SEQUENCE 有权
标题翻译：为ODD长度序列编码灰度代码序列
公开(公告)号：US20100134332A1
公开(公告)日：2010-06-03
申请号：US12699153
申请日：2010-02-03
申请人： Jayashri A. Basappa , Anil Pothireddy , David Grant Wheeler
发明人： Jayashri A. Basappa , Anil Pothireddy , David Grant Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.
摘要翻译：提供了一种装置，用于从具有长度“L”的二进制值序列生成灰度代码序列。因此，本发明的一个方面提供了一种电路，包括一个循环标志触发电路，其被配置为在第一值和第二值之间切换循环标志;耦合到循环标志触发电路的输出的中间值发生器，二进制值，并且被配置为从循环标志和二进制值生成中间值，以及耦合到中间值生成器的输出的二进制到灰色转换器，被配置为将中间值转换为灰度代码。

2. 发明授权

US07667629B2 Generating a gray code for an odd length sequence using a virtual space 失效
标题翻译：使用虚拟空间生成奇数长度序列的灰色代码
公开(公告)号：US07667629B2
公开(公告)日：2010-02-23
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

3. 发明申请

US20090295608A1 GENERATING A GRAY CODE FOR AN ODD LENGTH SEQUENCE USING A VIRTUAL SPACE 失效
标题翻译：使用虚拟空间生成ODD长度序列的灰度代码
公开(公告)号：US20090295608A1
公开(公告)日：2009-12-03
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

4. 发明授权

US08132036B2 Reducing latency in data transfer between asynchronous clock domains 失效
标题翻译：减少异步时钟域之间数据传输的延迟
公开(公告)号：US08132036B2
公开(公告)日：2012-03-06
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12 , H04L7/00 , G06F13/20
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

5. 发明申请

US20090271651A1 Method and System for Reducing Latency in Data Transfer Between Asynchronous Clock Domains 失效
标题翻译：减少异步时钟域之间数据传输延迟的方法和系统
公开(公告)号：US20090271651A1
公开(公告)日：2009-10-29
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

6. 发明授权

US07518535B1 Generating a Gray code sequence for any even length using an intermediate binary sequence 失效
标题翻译：使用中间二进制序列生成任何均匀长度的格雷码序列
公开(公告)号：US07518535B1
公开(公告)日：2009-04-14
申请号：US11954451
申请日：2007-12-12
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2−L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2−L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.
摘要翻译：为具有L个成员的循环序列生成用于非标准序列长度的灰色序列。对于具有小于L / 2的数值（C / 2-L）的循环序列的二进制成员，最高有效位被强制为逻辑“1”以创建中间二进制成员。对于大于或等于数量（C / 2-L）的成员添加到二进制文件中以创建中间二进制文件。然后将中间二进制变换为具有非标准序列长度L的格雷码序列。

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