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1. 发明授权

US07870448B2 In system diagnostics through scan matrix 失效
标题翻译：通过扫描矩阵进行系统诊断
公开(公告)号：US07870448B2
公开(公告)日：2011-01-11
申请号：US11958468
申请日：2007-12-18
申请人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
发明人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G06F11/267 , G01R31/318555
摘要： A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.
摘要翻译：公开了一种通过扫描矩阵进行系统诊断的方法，以及执行诊断的集成电路芯片。所述集成电路芯片可操作在多个边界扫描测试模式中，其中所述集成电路芯片中的至少一部分电路被测试，所述集成电路芯片包括扫描矩阵控制器和指令寄存器。提供扫描矩阵控制器用于将所述电路划分成多个矩阵，每个矩阵具有多个扫描元件。提供指令寄存器用于保持扫描矩阵控制器的指令，用于将芯片划分为所述多个矩阵。扫描矩阵控制器还被布置为通过将测试信号施加到电路的测试部分来根据指令寄存器中的指令来测试每个所述矩阵。

2. 发明授权

US09043180B2 Reducing power consumption during manufacturing test of an integrated circuit 有权
标题翻译：降低集成电路制造试验期间的功耗
公开(公告)号：US09043180B2
公开(公告)日：2015-05-26
申请号：US13369642
申请日：2012-02-09
申请人： Vikram Iyengar , Animesh Khare , Kenneth Pichamuthu
发明人： Vikram Iyengar , Animesh Khare , Kenneth Pichamuthu
IPC分类号： G01N33/48 , G01R31/3185
CPC分类号： G01R31/318314 , G01R31/318307 , G01R31/318575
摘要： Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.
摘要翻译：本发明的方面提供了在IC的制造测试期间降低功耗。在一个实施例中，本发明的方面包括一种用于在集成电路（IC）的制造测试期间降低功耗的方法，所述方法包括：提供多个域，每个域与时钟相关联; 将基于每个域的第一多个扫描链分组成第一测试组; 基于每个域将第二多个扫描链分组成第二测试组，其中第一测试组和第二测试组的分组包括确定可以同时测试哪些结构域; 并进行IC的制造测试。

3. 发明授权

US08130526B2 Programming a microchip ID register 失效
标题翻译：编程微芯片ID寄存器
公开(公告)号：US08130526B2
公开(公告)日：2012-03-06
申请号：US11837255
申请日：2007-08-10
申请人： Kelageri Nagaraj , Kenneth Pichamuthu , Prakash Venkitaraman , Baalaji Ramamoorthy Konda , Hari Krishnan Rajeev
发明人： Kelageri Nagaraj , Kenneth Pichamuthu , Prakash Venkitaraman , Baalaji Ramamoorthy Konda , Hari Krishnan Rajeev
IPC分类号： G11C5/02
CPC分类号： G11C16/20 , G11C29/12 , G11C29/1201 , G11C2029/4402
摘要： A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.
摘要翻译：公开了一种用于对微芯片的ID寄存器进行编程的方法。该方法包括在封装之前将至少一个附加ID引脚附接到微芯片的管芯的步骤。所述至少一个销被固定，使得当所述微芯片被封装时，所述至少一个销密封在所述封装内。通过向至少一个附加引脚提供二进制数据的多个独特组合来对至少一部分微芯片标识数据进行编程。二进制数据的每个独特组合对应于微芯片的唯一身份。至少一个引脚耦合到微芯片布局的相应模块，用于经由至少一个引脚提供与微芯片的特定身份相关联的信息。至少一个引脚还耦合到识别寄存器，以便在测试时将二进制数据的相应组合包括在微芯片的ID寄存器数据中。

4. 发明申请

US20090158105A1 IN SYSTEM DIAGNOSTICS THROUGH SCAN MATRIX 失效
标题翻译：通过扫描矩阵进行系统诊断
公开(公告)号：US20090158105A1
公开(公告)日：2009-06-18
申请号：US11958468
申请日：2007-12-18
申请人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
发明人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
IPC分类号： G01R31/3185 , G06F11/26
CPC分类号： G06F11/267 , G01R31/318555
摘要： A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.
摘要翻译：公开了一种通过扫描矩阵进行系统诊断的方法，以及执行诊断的集成电路芯片。所述集成电路芯片可操作在多个边界扫描测试模式中，其中所述集成电路芯片中的至少一部分电路被测试，所述集成电路芯片包括扫描矩阵控制器和指令寄存器。提供扫描矩阵控制器用于将所述电路划分成多个矩阵，每个矩阵具有多个扫描元件。提供指令寄存器用于保持扫描矩阵控制器的指令，用于将芯片划分为所述多个矩阵。扫描矩阵控制器还被布置为通过将测试信号施加到电路的测试部分来根据指令寄存器中的指令来测试每个所述矩阵。

5. 发明申请

US20130211769A1 REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路的制造测试期间降低功耗
公开(公告)号：US20130211769A1
公开(公告)日：2013-08-15
申请号：US13369642
申请日：2012-02-09
申请人： Vikram Iyengar , Animesh Khare , Kenneth Pichamuthu
发明人： Vikram Iyengar , Animesh Khare , Kenneth Pichamuthu
IPC分类号： G06F19/00
CPC分类号： G01R31/318314 , G01R31/318307 , G01R31/318575
摘要： Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.
摘要翻译：本发明的方面提供了在IC的制造测试期间降低功耗。在一个实施例中，本发明的方面包括一种用于在集成电路（IC）的制造测试期间降低功耗的方法，所述方法包括：提供多个域，每个域与时钟相关联; 将基于每个域的第一多个扫描链分组成第一测试组; 基于每个域将第二多个扫描链分组成第二测试组，其中第一测试组和第二测试组的分组包括确定可以同时测试哪些结构域; 并进行IC的制造测试。

6. 发明授权

US07900112B2 System and method for digital logic testing 有权
标题翻译：数字逻辑测试的系统和方法
公开(公告)号：US07900112B2
公开(公告)日：2011-03-01
申请号：US12173651
申请日：2008-07-15
申请人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
发明人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
IPC分类号： G01R31/28
CPC分类号： G06F11/261 , G01R31/318385 , G01R31/318511 , G06F11/263
摘要： Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
摘要翻译：一些实施例提供了一种用于测试逻辑的数字逻辑设计和数字逻辑测试的方法，包括锁存器的锁存器，包括测量锁存器的锁存器，其是比其他锁存器更多地测量局部故障的锁存器，以及护理位锁存器，需要特定的输入值来测试故障，其中焦点故障是被测逻辑中随机选择的未测试故障，该方法包括产生被测逻辑的测试模式; 模拟测试逻辑上的测试模式的故障; 基于他们分别测量的局灶性故障数量的排序测量锁存器; 并从至少一些最高排名的测量锁存器中追溯多个级别，并插入测试观察锁存器。还提供了其他方法和系统。

7. 发明申请

US20100017668A1 SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING 有权
标题翻译：数字逻辑测试系统与方法
公开(公告)号：US20100017668A1
公开(公告)日：2010-01-21
申请号：US12173651
申请日：2008-07-15
申请人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
发明人： Kenneth Pichamuthu , Prakash Venkitaraman , Andrew Ferko
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G01R31/318385 , G01R31/318511 , G06F11/263
摘要： Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
摘要翻译：一些实施例提供了一种用于测试逻辑的数字逻辑设计和数字逻辑测试的方法，包括锁存器的锁存器，包括测量锁存器的锁存器，其是比其他锁存器更多地测量局部故障的锁存器，以及护理位锁存器，需要特定的输入值来测试故障，其中焦点故障是被测逻辑中随机选择的未测试故障，该方法包括产生被测逻辑的测试模式; 模拟测试逻辑上的测试模式的故障; 基于他们分别测量的局灶性故障数量的排序测量锁存器; 并从至少一些最高排名的测量锁存器中追溯多个级别，并插入测试观察锁存器。还提供了其他方法和系统。

8. 发明申请

US20090039347A1 PROGRAMMING A MICROCHIP ID REGISTER 失效
标题翻译：编程MICROCHIP ID寄存器
公开(公告)号：US20090039347A1
公开(公告)日：2009-02-12
申请号：US11837255
申请日：2007-08-10
申请人： Kelageri Nagaraj , Kenneth Pichamuthu , Prakash Venkitaraman , Baalaji Ramamoorthy Konda , Hari Krishnan Rajeev
发明人： Kelageri Nagaraj , Kenneth Pichamuthu , Prakash Venkitaraman , Baalaji Ramamoorthy Konda , Hari Krishnan Rajeev
IPC分类号： H01L23/58 , H01L21/71
CPC分类号： G11C16/20 , G11C29/12 , G11C29/1201 , G11C2029/4402
摘要： A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.
摘要翻译：公开了一种用于对微芯片的ID寄存器进行编程的方法。该方法包括在封装之前将至少一个附加ID引脚附接到微芯片的管芯的步骤。所述至少一个销被固定，使得当所述微芯片被封装时，所述至少一个销密封在所述封装内。通过向至少一个附加引脚提供二进制数据的多个唯一组合来对至少一部分微芯片标识数据进行编程。二进制数据的每个独特组合对应于微芯片的唯一身份。至少一个引脚耦合到微芯片布局的相应模块，用于经由至少一个引脚提供与微芯片的特定身份相关联的信息。至少一个引脚还耦合到识别寄存器，以便在测试时将二进制数据的相应组合包括在微芯片的ID寄存器数据中。

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