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1. 发明授权

US08199739B2 Return link time adjustments in FDD OFDMA or SC-FDM systems 有权
标题翻译：在FDD OFDMA或SC-FDM系统中返回链路时间调整
公开(公告)号：US08199739B2
公开(公告)日：2012-06-12
申请号：US12408355
申请日：2009-03-20
申请人： Hemanth Sampath , Jeremy H. Lin , Sunil K. Kandukuri Narayan , Sameer Vermani
发明人： Hemanth Sampath , Jeremy H. Lin , Sunil K. Kandukuri Narayan , Sameer Vermani
IPC分类号： H04J1/00
CPC分类号： H04L27/2607 , H04L27/2655
摘要： A method for adjusting timing in a Frequency Division Multiplexing (FDM) system, including receiving a request to perform a timing correction, generating a time domain FDM symbol, and controlling the timing correction in the time domain FDM symbol by at least one of adjusting a length of a cyclic prefix, overlapping a portion of adjacent FDM symbols, adjusting a symbol windowing length, or utilizing a return link (RL) silence interval.
摘要翻译：一种用于在频分复用（FDM）系统中调整定时的方法，包括接收执行定时校正的请求，产生时域FDM符号，以及通过以下步骤中的至少一个来控制时域FDM符号中的定时校正：循环前缀的长度，与相邻FDM符号的一部分重叠，调整符号加窗长度，或利用返回链路（RL）静默间隔。

2. 发明申请

US20090245334A1 WALL CLOCK TIMER AND SYSTEM FOR GENERIC MODEM 失效
标题翻译：一般调制解调器的时钟定时器和系统
公开(公告)号：US20090245334A1
公开(公告)日：2009-10-01
申请号：US12261937
申请日：2008-10-30
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
IPC分类号： H04B1/38
CPC分类号： H04B1/406
摘要： A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.
摘要翻译：调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。每个WCSMSC接收由多个可编程定时器中相应的一个产生的控制信号。每个定时器从挂钟计数器接收相同的计数值序列。控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。处理器还可以编程定时器以产生周期性控制信号。当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

3. 发明申请

US20090245222A1 RETURN LINK TIME ADJUSTMENTS IN FDD OFDMA OR SC-FDM SYSTEMS 有权
标题翻译：在FDD OFDMA或SC-FDM系统中返回链路时间调整
公开(公告)号：US20090245222A1
公开(公告)日：2009-10-01
申请号：US12408355
申请日：2009-03-20
申请人： Hemanth Sampath , Jeremy H. Lin , Sunil K. Kandukuri Narayan , Sameer Vermani
发明人： Hemanth Sampath , Jeremy H. Lin , Sunil K. Kandukuri Narayan , Sameer Vermani
IPC分类号： H04J1/00
CPC分类号： H04L27/2607 , H04L27/2655
摘要： A method for adjusting timing in a Frequency Division Multiplexing (FDM) system, including receiving a request to perform a timing correction, generating a time domain FDM symbol, and controlling the timing correction in the time domain FDM symbol by at least one of adjusting a length of a cyclic prefix, overlapping a portion of adjacent FDM symbols, adjusting a symbol windowing length, or utilizing a return link (RL) silence interval.
摘要翻译：一种用于在频分复用（FDM）系统中调整定时的方法，包括接收执行定时校正的请求，产生时域FDM符号，以及通过以下步骤中的至少一个来控制时域FDM符号中的定时校正：循环前缀的长度，与相邻FDM符号的一部分重叠，调整符号加窗长度，或利用返回链路（RL）静默间隔。

4. 发明申请

US20090209272A1 EFFICIENT SLEEP MODE OPERATION FOR OFDMA SYSTEMS 有权
标题翻译： OFDMA系统的高效休眠模式操作
公开(公告)号：US20090209272A1
公开(公告)日：2009-08-20
申请号：US12032467
申请日：2008-02-15
申请人： Ravi Palanki , Jeremy H. Lin , Hemanth Sampath
发明人： Ravi Palanki , Jeremy H. Lin , Hemanth Sampath
IPC分类号： H04B1/50
CPC分类号： H04L27/2655 , H04B2201/70709 , H04L27/2649 , H04W52/0235 , Y02D70/00
摘要： A communications system and method for a wireless mobile device is provided. The method includes performing sleep mode operations in a device and performing wake-up operations with one or more base stations in view of the sleep mode operations in the device. The method also includes demodulating a communications channel for the device during sleep mode operations in the device and prior to synchronizing with the base stations.
摘要翻译：提供了一种用于无线移动设备的通信系统和方法。该方法包括在设备中执行休眠模式操作并且考虑到设备中的睡眠模式操作来执行与一个或多个基站的唤醒操作。该方法还包括在设备中的睡眠模式操作期间以及在与基站同步之前解调设备的通信信道。

5. 发明授权

US07209461B2 Method and apparatus for chip-rate processing in a CDMA system 有权
标题翻译：用于CDMA系统中码片速率处理的方法和装置
公开(公告)号：US07209461B2
公开(公告)日：2007-04-24
申请号：US09852436
申请日：2001-05-09
申请人： Avneesh Agrawal , Jeremy H. Lin
发明人： Avneesh Agrawal , Jeremy H. Lin
IPC分类号： H04B7/216
CPC分类号： H04B1/7117 , H04B1/7115 , H04B2201/70707
摘要： Techniques for increased finger demodulation capability in a hardware efficient manner are disclosed. In one aspect, I and Q samples are shifted into a parallel-accessible shift register. A plurality of chip samples are accessed from the shift register and operated on in parallel to produce a multi-chip result for a channel each cycle. These multi-chip results can be accumulated and output to a symbol-rate processor on symbol boundaries. The scheduling of shift register access, computation, and accumulation can be scheduled such that the hardware is time-shared to support a large number of channels. In another aspect, time-tracking of a large number of channels can be accommodated through channel-specific indexing of the contents of the shift register file. These aspects, along with various others also presented, provide for hardware efficient chip rate processing capability for a large number of channels, with a high degree of flexibility in deployment of those channels.
摘要翻译：公开了以硬件有效的方式增加手指解调能力的技术。在一个方面，I和Q样本被移入并行可访问的移位寄存器。从移位寄存器访问多个芯片样本，并行操作，以产生每个周期的信道的多芯片结果。这些多芯片结果可以被累加并输出到符号边界上的符号速率处理器。可以调度移位寄存器访问，计算和累加的调度，使得硬件是时分的，以支持大量信道。在另一方面，可以通过针对移位寄存器文件的内容的特定索引来容纳大量信道的时间跟踪。这些方面以及还提出了各种其他方面，为大量渠道提供硬件高效的芯片速率处理能力，在这些频道的部署方面具有高度的灵活性。

6. 发明授权

US08873671B2 Method and system for LLR buffer reduction in a wireless communication modem 有权
标题翻译：无线通信调制解调器中LLR缓冲区减少的方法和系统
公开(公告)号：US08873671B2
公开(公告)日：2014-10-28
申请号：US12405649
申请日：2009-03-17
申请人： Hemanth Sampath , Avneesh Agrawal , Jeremy H. Lin
发明人： Hemanth Sampath , Avneesh Agrawal , Jeremy H. Lin
IPC分类号： H04L27/00 , H04L1/00 , H03M13/00 , H04L25/06 , H03M13/45 , H04L5/00 , H04L1/18
CPC分类号： H03M13/45 , H03M13/6588 , H04L1/0046 , H04L1/1819 , H04L1/1822 , H04L1/1835 , H04L1/1845 , H04L5/0007 , H04L25/067
摘要： A system involves a transmitting device (for example, a first wireless communication device) and a receiving device (for example, a second wireless communication device). In the receiving device, LLR (Log-Likelihood Ratio) values are stored into an LLR buffer. LLR bit width is adjusted as a function of packet size of an incoming transmission to reduce the LLR buffer size required and/or to prevent LLR buffer capacity from being exceeded. The receiver may use a higher performance demodulator in order to maintain performance despite smaller LLR bit width. In the transmitting device, encoder code rate is adjusted as a function of receiver LLR buffer capacity and packet size of the outgoing transmission such that receiver LLR buffer capacity is not exceeded. Any combination of receiver LLR bit width adjustment, demodulator selection, and encoder code rate adjustment can be practiced to reduce LLR buffer size required while maintaining performance.
摘要翻译：系统涉及发送设备（例如，第一无线通信设备）和接收设备（例如，第二无线通信设备）。在接收设备中，将LLR（对数似然比）值存储到LLR缓冲器中。根据输入传输的分组大小调整LLR比特宽度，以减少所需的LLR缓冲区大小和/或防止超出LLR缓冲区容量。接收机可以使用更高性能的解调器，以便尽管较小的LLR位宽度来保持性能。在发送设备中，根据接收机LLR缓冲器容量和输出传输的分组大小调节编码器码率，使得接收机LLR缓冲器容量不被超过。可以实现接收机LLR位宽度调整，解调器选择和编码器码率调整的任何组合，以在保持性能的同时减少所需的LLR缓冲区大小。

7. 发明授权

US08787989B2 Efficient sleep mode operation for OFDMA systems 有权
标题翻译： OFDMA系统的高效休眠模式操作
公开(公告)号：US08787989B2
公开(公告)日：2014-07-22
申请号：US12032467
申请日：2008-02-15
申请人： Ravi Palanki , Jeremy H. Lin , Hemanth Sampath
发明人： Ravi Palanki , Jeremy H. Lin , Hemanth Sampath
IPC分类号： H04B1/38
CPC分类号： H04L27/2655 , H04B2201/70709 , H04L27/2649 , H04W52/0235 , Y02D70/00
摘要： A communications system and method for a wireless mobile device is provided. The method includes performing sleep mode operations in a device and performing wake-up operations with one or more base stations in view of the sleep mode operations in the device. The method also includes demodulating a communications channel for the device during sleep mode operations in the device and prior to synchronizing with the base stations.
摘要翻译：提供了一种用于无线移动设备的通信系统和方法。该方法包括在设备中执行休眠模式操作并且考虑到设备中的睡眠模式操作来执行与一个或多个基站的唤醒操作。该方法还包括在设备中的睡眠模式操作期间以及在与基站同步之前解调设备的通信信道。

8. 发明授权

US08738680B2 Reuse engine with task list for fast fourier transform and method of using the same 有权
标题翻译：使用任务列表重新使用引擎进行快速傅立叶变换和使用相同的方法
公开(公告)号：US08738680B2
公开(公告)日：2014-05-27
申请号：US12411728
申请日：2009-03-26
申请人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
发明人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

9. 发明授权

US08566676B2 FEC code and code rate selection based on packet size 有权
标题翻译：基于分组大小的FEC码和码率选择
公开(公告)号：US08566676B2
公开(公告)日：2013-10-22
申请号：US11943172
申请日：2007-11-20
申请人： Ravi Palanki , Jeremy H. Lin , Aamod Khandekar , Alexei Gorokhov , Avneesh Agrawal
发明人： Ravi Palanki , Jeremy H. Lin , Aamod Khandekar , Alexei Gorokhov , Avneesh Agrawal
IPC分类号： H03M13/00
CPC分类号： H04L1/0007 , H04L1/0009 , H04L1/0021 , H04L1/0042 , H04L1/1812 , H04L1/1822
摘要： Techniques for encoding and decoding data are described. In an aspect, multiple code rates for a forward error correction (FEC) code may be supported, and a suitable code rate may be selected based on packet size. A transmitter may obtain at least one threshold to use for code rate selection, determine a packet size to use for data transmission, and select a code rate from among the multiple code rates based on the packet size and the at least one threshold. In another aspect, multiple FEC codes of different types (e.g., Turbo, LDPC, and convolutional codes) may be supported, and a suitable FEC code may be selected based on packet size. The transmitter may obtain at least one threshold to use for FEC code selection and may select an FEC code from among the multiple FEC codes based on the packet size and the at least one threshold.
摘要翻译：描述用于编码和解码数据的技术。在一方面，可以支持用于前向纠错（FEC）码的多个码率，并且可以基于分组大小来选择合适的码率。发射机可以获得用于码率选择的至少一个阈值，确定用于数据传输的分组大小，并且基于分组大小和至少一个阈值从多个码率中选择码率。在另一方面，可以支持不同类型的多个FEC码（例如，Turbo，LDPC和卷积码），并且可以基于分组大小来选择合适的FEC码。发射机可以获得用于FEC码选择的至少一个阈值，并且可以基于分组大小和至少一个阈值从多个FEC码中选择FEC码。

10. 发明授权

US08458380B2 Off-line task list architecture utilizing tightly coupled memory system 有权
标题翻译：使用紧密耦合的存储器系统的离线任务列表架构
公开(公告)号：US08458380B2
公开(公告)日：2013-06-04
申请号：US12396217
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
IPC分类号： G06F3/00 , G06F9/46
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

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