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1. 发明授权

US08458380B2 Off-line task list architecture utilizing tightly coupled memory system 有权
标题翻译：使用紧密耦合的存储器系统的离线任务列表架构
公开(公告)号：US08458380B2
公开(公告)日：2013-06-04
申请号：US12396217
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
IPC分类号： G06F3/00 , G06F9/46
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

2. 发明申请

US20090248920A1 Off-Line Task List Architecture 有权
标题翻译：离线任务列表架构
公开(公告)号：US20090248920A1
公开(公告)日：2009-10-01
申请号：US12396217
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski , Kevin W. Yen
IPC分类号： G06F3/00 , G06F1/04 , G06F12/08
CPC分类号： G06F9/3879 , G06F15/7814
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

3. 发明申请

US20090245334A1 WALL CLOCK TIMER AND SYSTEM FOR GENERIC MODEM 失效
标题翻译：一般调制解调器的时钟定时器和系统
公开(公告)号：US20090245334A1
公开(公告)日：2009-10-01
申请号：US12261937
申请日：2008-10-30
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
IPC分类号： H04B1/38
CPC分类号： H04B1/406
摘要： A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.
摘要翻译：调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。每个WCSMSC接收由多个可编程定时器中相应的一个产生的控制信号。每个定时器从挂钟计数器接收相同的计数值序列。控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。处理器还可以编程定时器以产生周期性控制信号。当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

4. 发明授权

US08787433B2 Wall clock timer and system for generic modem 失效
标题翻译：墙钟计时器和通用调制解调器系统
公开(公告)号：US08787433B2
公开(公告)日：2014-07-22
申请号：US12261937
申请日：2008-10-30
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Remi Gurski
IPC分类号： H04B1/38 , H04L12/28
CPC分类号： H04B1/406
摘要： A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.
摘要翻译：调制解调器（例如，蜂窝电话中的调制解调器）包括多个无线通信系统调制解调器子电路（WCSMSC）。每个WCSMSC接收由多个可编程定时器中相应的一个产生的控制信号。每个定时器从挂钟计数器接收相同的计数值序列。控制整个调制解调器操作的处理器可以编程定时器以在挂钟计数器的特定计数时间产生控制脉冲。处理器还可以编程定时器以产生周期性控制信号。当各种WCSMSC在帧的处理中开始运行时，从定时器输出的控制信号协调编排。通过定时器的可编程性，挂钟计时器系统可编程以产生定制的控制信号，使得具有任意帧结构的新协议和不同协议的帧可以由相同的调制解调器/定时器系统来处理。

5. 发明申请

US20090248774A1 REUSE ENGINE WITH TASK LIST FOR FAST FOURIER TRANSFORM AND METHOD OF USING THE SAME 有权
标题翻译：用快速傅里叶变换的任务列表重新使用发动机及其使用方法
公开(公告)号：US20090248774A1
公开(公告)日：2009-10-01
申请号：US12411728
申请日：2009-03-26
申请人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
发明人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

6. 发明授权

US08520571B2 Reconfigurable wireless modem sub-circuits to implement multiple air interface standards 有权
标题翻译：可重配置的无线调制解调器子电路实现多个空中接口标准
公开(公告)号：US08520571B2
公开(公告)日：2013-08-27
申请号：US12396270
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali RostamPisheh , Raghu Challa , Hemanth Sampath , Megan Wu , Joseph Zanotelli , Mrinal Nath
IPC分类号： H04B7/00
CPC分类号： G06F15/7842
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

7. 发明授权

US08738680B2 Reuse engine with task list for fast fourier transform and method of using the same 有权
标题翻译：使用任务列表重新使用引擎进行快速傅立叶变换和使用相同的方法
公开(公告)号：US08738680B2
公开(公告)日：2014-05-27
申请号：US12411728
申请日：2009-03-26
申请人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
发明人： Arunava Chaudhuri , Hemanth Sampath , Iwen Yao , Jeremy H. Lin , Raghu N. Challa , Min Wu
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L5/0007 , H04L5/0023 , H04L5/0053 , H04L27/265 , H04L27/2662
摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.
摘要翻译：用于执行傅里叶变换的改进的处理引擎包括配置成处理顺序指令软件命令的指令处理器和耦合到指令处理器的傅里叶变换引擎。傅立叶变换引擎被配置为对串行数据流执行傅里叶变换。傅里叶变换引擎被配置为经由一组软件任务从指令处理器接收配置信息和操作数据。

8. 发明申请

US20090245192A1 Reconfigurable Wireless Modem Sub-Circuits To Implement Multiple Air Interface Standards 有权
标题翻译：可重构无线调制解调器子电路实现多个空中接口标准
公开(公告)号：US20090245192A1
公开(公告)日：2009-10-01
申请号：US12396270
申请日：2009-03-02
申请人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali Rostampisheh , Raghu Challa , Hamanth Sampath , Min Wu , Joseph Zanotelli , Mrinal M. Nath
发明人： Arunava Chaudhuri , Iwen Yao , Jeremy H. Lin , Ali Rostampisheh , Raghu Challa , Hamanth Sampath , Min Wu , Joseph Zanotelli , Mrinal M. Nath
IPC分类号： H04W88/16 , G06F9/46
CPC分类号： G06F15/7842
摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.
摘要翻译：灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。子电路的任务管理器可以配置和控制子电路的可配置硬件。中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。每个任务列表包括相应子电路的任务指令。子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

9. 发明申请

US20090245091A1 BUFFERED DEMOD AND DEMAP FUNCTIONS 失效
标题翻译：缓冲的演示和演示功能
公开(公告)号：US20090245091A1
公开(公告)日：2009-10-01
申请号：US12407482
申请日：2009-03-19
申请人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
发明人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
IPC分类号： H04J11/00
CPC分类号： H04L25/0202 , H04L5/0007 , H04L5/0023 , H04L27/265
摘要： An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.
摘要翻译：一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。信道估计装置还可以向共享缓冲器提供中间数据。中间数据可以是瓦片形式，并且可以从FFT符号数据导出。此外，中间数据可以存储在共享缓冲器中。解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。

10. 发明授权

US08520500B2 Buffered demod and demap functions 失效
标题翻译：缓冲解调和解映射功能
公开(公告)号：US08520500B2
公开(公告)日：2013-08-27
申请号：US12407482
申请日：2009-03-19
申请人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
发明人： Jeremy H. Lin , Arunava Chaudhuri , Raghu N. Challa , Hemanth Sampath
IPC分类号： H04J11/00
CPC分类号： H04L25/0202 , H04L5/0007 , H04L5/0023 , H04L27/265
摘要： An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.
摘要翻译：一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。信道估计装置还可以向共享缓冲器提供中间数据。中间数据可以是瓦片形式，并且可以从FFT符号数据导出。此外，中间数据可以存储在共享缓冲器中。解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。

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