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1. 发明授权

US06614714B2 Semiconductor memory system having a data clock system for reliable high-speed data transfers 失效
标题翻译：具有用于可靠的高速数据传输的数据时钟系统的半导体存储器系统
公开(公告)号：US06614714B2
公开(公告)日：2003-09-02
申请号：US10055149
申请日：2002-01-22
申请人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
发明人： Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska , Li-Kong Wang
IPC分类号： G11C818
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
摘要翻译：提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近，至少一个时钟驱动器位于第二时钟路径的近端附近。

2. 发明授权

US06449202B1 DRAM direct sensing scheme 失效
标题翻译： DRAM直接感测方案
公开(公告)号：US06449202B1
公开(公告)日：2002-09-10
申请号：US09929593
申请日：2001-08-14
申请人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C11/4091
摘要： A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage. An nFET writeback device is coupled between the data line and the bitline which is switched on to begin a data writeback into the memory cell when the signal develops on the data line.
摘要翻译：一种直接感测电路和方法，用于在数据读取操作中在数据线上从连接到位线的存储器单元读取数据，并且将数据线开放位线检测而不使用参考位线信号。在数据读取操作之前，位线和数据线都被预充电到预充电电压，并且感测节点被预充电到地。 pFET器件的栅极耦合到从存储器单元在位线上产生的信号，以检测和放大其信号电平，并且其源极耦合到耦合到感测节点的电压源及其漏极，使得信号发展位线决定了pFET器件导通的程度。 nFET器件的栅极耦合到感测节点以检测和放大其信号电平，并且其漏极耦合到数据线。当感测到低数据信号时，在位线上产生的信号导致通过pFET器件的阈值电压漏电流，以对nFET器件的栅极进行充电，该nFET器件的栅极被浮置以放大在位线上产生的信号，以将预充电的数据线拉下来。当感测高数据信号时，pFET器件和nFET器件保持不激活，并且数据线保持在其预充电高电压。当在数据线上产生信号时，nFET写回装置耦合在数据线和打开的位线之间，以开始对存储器单元的数据写回。

3. 发明授权

US06261914B1 Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer 失效
标题翻译：使用自对准抛光速率增强层改善化学机械抛光的局部均匀性的方法
公开(公告)号：US06261914B1
公开(公告)日：2001-07-17
申请号：US09361961
申请日：1999-07-27
申请人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Carl J. Radens , Jeremy K. Stephens
发明人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Carl J. Radens , Jeremy K. Stephens
IPC分类号： H01L21331
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).
摘要翻译：一种制造半导体器件的方法，包括在硅衬底上形成氧化物层，在所述氧化物层上形成氮化物层; 在氮化物层上沉积掺杂氧化物层和未掺杂的多孔氧化物层之一，蚀刻通过掺杂层和未掺杂的多孔氧化物层，氮化物层和氧化物层之一的沟槽，沉积未填充的氧化物层以填充沟槽，并通过化学机械抛光（CMP）图案化未掺杂的氧化物。

4. 发明授权

US06711078B2 Writeback and refresh circuitry for direct sensed DRAM macro 有权
标题翻译：用于直接感测DRAM宏的回写和刷新电路
公开(公告)号：US06711078B2
公开(公告)日：2004-03-23
申请号：US10064306
申请日：2002-07-01
申请人： Ciaran J. Brennan , John A. Fifield , Jeremy K. Stephens , Daniel W. Storaska
发明人： Ciaran J. Brennan , John A. Fifield , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： B11C700
CPC分类号： G11C11/40615 , G11C7/065 , G11C7/1051 , G11C7/1069 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.
摘要翻译：用于直接感测架构存储器的回写和刷新电路，其中多个主感测放大器连接到全局数据线，并且还连接到位线，每个位线被耦合到被选择用于写入和读取操作的存储器存储单元的阵列通过多个字线。单个次级感测放大器从全局数据线上的主感测放大器接收模拟电平数据，并且包括恢复/回写电路，其对数据进行数字化，然后将数字化数据通过全局数据线返回到主感测放大器并且返回记忆。每个存储器读取周期，第一周期读取操作和第二个周期回写操作都使用2周期读/写操作。 2周期的破坏性读取架构不需要缓存和复杂的缓存算法。

5. 发明授权

US06420216B1 Fuse processing using dielectric planarization pillars 失效
标题翻译：使用介质平面化柱的保险丝处理
公开(公告)号：US06420216B1
公开(公告)日：2002-07-16
申请号：US09525729
申请日：2000-03-14
申请人： Larry Clevenger , Louis L. C. Hsu , Chandrasekhar Narayan , Jeremy K. Stephens , Michael Wise
发明人： Larry Clevenger , Louis L. C. Hsu , Chandrasekhar Narayan , Jeremy K. Stephens , Michael Wise
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.
摘要翻译：电熔丝结构包括半导体衬底; 半导体衬底上的至少一个电绝缘层，其中其一部分包含电布线，另一个相邻部分基本上不含电线; 可选地，在所述至少一个电绝缘层上的另一个电绝缘层。电绝缘层具有形成在基本上不含电线的部分上的凹陷，凹陷具有比电绝缘层的相邻部分更低的表面水平。保险丝结构还包括设置在凹部上方的保险丝绝缘体和熔丝绝缘体上的保险丝。优选地，熔丝绝缘体仅设置在凹陷中，以将熔丝升高到与电绝缘层的相邻部分相同的高度。熔丝结构可以具有单层，或者包括具有与激光束不同程度的反射率的交替层，例如氧化硅和氮化硅的交替层。优选的熔丝结构包括凹陷中的电阻和耐热熔断绝缘体，使得熔丝绝缘体基本上防止指向熔丝的能量束的热量传递到半导体衬底。更优选地，形成的保险丝的宽度小于保险丝绝缘体的宽度。熔丝结构还可以包括在与绝缘层相同的电绝缘层上的附加布线。

6. 发明授权

US06552944B2 Single bitline direct sensing architecture for high speed memory device 有权
标题翻译：用于高速存储器件的单位线直接感测架构
公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
申请人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
发明人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译：单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。数据线优选地布置在多个存储器阵列上。读取和写入操作可能共享或不共享数据行。一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。可以使用简单的逆变器来检测由电阻比确定的数据线的电平。以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。

7. 发明授权

US06348395B1 Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow 失效
标题翻译：金刚石作为抛光停止层，用于镶嵌工艺流程中的化学 - 机械平面化
公开(公告)号：US06348395B1
公开(公告)日：2002-02-19
申请号：US09589818
申请日：2000-06-07
申请人： Lawrence A. Clevenger , Louis L. C. Hsu , Jeremy K. Stephens , Michael Wise
发明人： Lawrence A. Clevenger , Louis L. C. Hsu , Jeremy K. Stephens , Michael Wise
IPC分类号： H01L2176
CPC分类号： H01L21/31053 , H01L21/28525 , H01L21/3081 , H01L21/31144 , H01L21/3212 , H01L21/7684
摘要： A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in a sufficient decrease in topography at the surface of the inter-level dielectric.
摘要翻译：使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光在图案化过程中。在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

8. 发明授权

US06232222B1 Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
标题翻译：使用阻挡掩模和所得半导体结构消除临界掩模的方法
公开(公告)号：US06232222B1
公开(公告)日：2001-05-15
申请号：US09395418
申请日：1999-09-14
申请人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
发明人： Michael Armacost , Richard A. Conti , Jeffrey P. Gambino , Jeremy K. Stephens
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31144 , H01L27/10873 , H01L27/10894
摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.
摘要翻译：形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模。临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。

9. 发明授权

US6129610A Polish pressure modulation in CMP to preferentially polish raised features 有权
标题翻译： CMP中的波兰压力调制优先抛光凸起特征
公开(公告)号：US6129610A
公开(公告)日：2000-10-10
申请号：US134718
申请日：1998-08-14
申请人： Jeremy K. Stephens
发明人： Jeremy K. Stephens
IPC分类号： B24B1/00 , B24B37/04 , B24B49/16
CPC分类号： B24B1/00 , B24B37/04 , B24B49/16
摘要： A chemical-mechanical planarization (CMP) process is provided whereby cyclical pressure means varies the force against the wafer and polishing pad during the planarizing operation with the planarizing pad specially defined to have a relaxation time which is correlated with the force cycle so that the planarizing is enhanced. The relaxation time of the pad is greater than the downward an/or upward force cycle time on the wafer or pad and provides a planarizing process wherein the height of the pad during planarization is intermediate between a decompressed pad position and a compressed pad position typically encountered in a conventional CMP process.
摘要翻译：提供化学机械平面化（CMP）工艺，其中循环压力装置在平坦化操作期间改变对晶片和抛光垫的力，其中平面化垫特别定义为具有与力循环相关的松弛时间，使得平面化增强了。焊盘的松弛时间大于晶片或焊盘上的向下或向上的力循环时间，并且提供平坦化处理，其中在平坦化期间焊盘的高度位于通常遇到的压缩焊盘位置和压缩焊盘位置之间在常规CMP工艺中。

10. 发明授权

US6102776A Apparatus and method for controlling polishing of integrated circuit substrates 有权
标题翻译：用于控制集成电路基板的抛光的装置和方法
公开(公告)号：US6102776A
公开(公告)日：2000-08-15
申请号：US225597
申请日：1999-01-06
申请人： Karl E. Boggs , Kenneth M. Davis , William F. Landers , Robert M. Merkling, Jr. , Michael L. Passow , Jeremy K. Stephens
发明人： Karl E. Boggs , Kenneth M. Davis , William F. Landers , Robert M. Merkling, Jr. , Michael L. Passow , Jeremy K. Stephens
IPC分类号： B24B37/013 , B24B49/04 , B24B49/10 , B24B49/00 , B24B51/00
CPC分类号： B24B37/013 , B24B49/04 , B24B49/10
摘要： A system for polishing a surface. The surface is positioned in contact with a rotating table having a polishing slurry or compound applied to a table surface. The pattern formed in the polishing compound as the table is rotated is monitored, and when the pattern dimensions reach a predetermined size, indicating a polished end point, the polisher ends polishing.
摘要翻译：用于抛光表面的系统。表面定位成与具有施加到台面的抛光浆料或化合物的旋转台接触。监视在作为工作台的抛光组合物中形成的图案旋转，并且当图案尺寸达到预定尺寸时，指示抛光的终点，抛光机结束抛光。

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