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1. 发明授权

US09429968B2 Power-gated electronic device 有权
标题翻译：电源门控电子设备
公开(公告)号：US09429968B2
公开(公告)日：2016-08-30
申请号：US13446378
申请日：2012-04-13
申请人： Johannes Gerber , Frank Dornseifer
发明人： Johannes Gerber , Frank Dornseifer
IPC分类号： H02J9/00 , G05F1/56 , G06F1/26
CPC分类号： G05F1/56 , G06F1/26 , G06F1/263
摘要： A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply (LDO), an auxiliary power supply and at least one electronic domain having a power gate. The LDO provides a supply voltage to the at least one electronic domain which is coupled to a supply rail of the LDO via a switch, acting as a power gate. The auxiliary power supply comprises at least one current source which is coupled to the electronic domain via an auxiliary switch acting as an auxiliary power gate. The auxiliary power supply is configured to control the auxiliary switch as a function of a voltage difference between a reference voltage and the auxiliary supply voltage.
摘要翻译：提供了一种电源门控电子设备及其操作方法。电源门控电子设备包括低压降电源（LDO），辅助电源和至少一个具有电源门的电子域。 LDO向至少一个电子域提供电源电压，该至少一个电子域经由用作功率门的开关耦合到LDO的电源轨。辅助电源包括至少一个电流源，其经由用作辅助电源门的辅助开关耦合到电子域。辅助电源被配置为根据参考电压和辅助电源电压之间的电压差来控制辅助开关。

2. 发明授权

US08750015B2 Integrated circuit comprising a FRAM memory and method for granting read-access to a FRAM memory 有权
标题翻译：包括FRAM存储器的集成电路和用于授予对FRAM存储器的读取访问的方法
公开(公告)号：US08750015B2
公开(公告)日：2014-06-10
申请号：US13025878
申请日：2011-02-11
申请人： Volker Rzehak , Rudiger Kuhn , Johannes Gerber , Matthias Arnold
发明人： Volker Rzehak , Rudiger Kuhn , Johannes Gerber , Matthias Arnold
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273
摘要： An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor which is then disconnected from the integrated circuit power supply. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged and disconnected from the power supply. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.
摘要翻译：电子设备包括具有FRAM存储器的集成电路和连接在用于FRAM存储器和接地的电源之间的集成电容器。集成电容器具有足以存储FRAM存储器的完整读/写周期所需的电荷的电容。当对FRAM存储器进行读取访问时，FRAM存储器由集成电容器提供，然后与集成电路电源断开连接。在接收到对FRAM存储器的读取访问的请求时，充电检测器检测对于FRAM存储器的完整的读/写周期，内部电容器是否被充分充电。仅当内部电容器充分充电并与电源断开连接时，才可以对FRAM存储器进行读取。替代实施例从两个集成电容器交替地对FRAM充电和供电。

3. 发明申请

US20130114324A1 Integrated Circuit Comprising a FRAM Memory and Method for Granting Read-Access to a FRAM Memory 有权
标题翻译：包含FRAM存储器的集成电路和授予对FRAM存储器的读取访问的方法
公开(公告)号：US20130114324A1
公开(公告)日：2013-05-09
申请号：US13025878
申请日：2011-02-11
申请人： Volker Rzehak , Rudiger Kuhn , Johannes Gerber , Matthias Arnold
发明人： Volker Rzehak , Rudiger Kuhn , Johannes Gerber , Matthias Arnold
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/22 , G11C11/2273
摘要： An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access to the FRAM memory, the FRAM memory is supplied by the integrated capacitor. Upon receiving a request for a read-access to the FRAM memory, a charge detector detects whether the internal capacitor is sufficiently charged for a complete read-and-write-back cycle of the FRAM memory. Read-access to the FRAM memory is only granted if the internal capacitor is sufficiently charged. An alternative embodiment alternately charges and powers the FRAM from two integrated capacitors.
摘要翻译：电子设备包括具有FRAM存储器的集成电路和连接在用于FRAM存储器和接地的电源之间的集成电容器。集成电容器具有足以存储FRAM存储器的完整读/写周期所需的电荷的电容。当对FRAM存储器进行读取访问时，FRAM存储器由集成电容器提供。在接收到对FRAM存储器的读取访问的请求时，充电检测器检测对于FRAM存储器的完整的读/写周期，内部电容器是否被充分充电。只有内部电容充足电才可以对FRAM存储器进行读取。替代实施例从两个集成电容器交替地对FRAM充电和供电。

4. 发明授权

US08373459B2 Power-on reset circuit 有权
标题翻译：上电复位电路
公开(公告)号：US08373459B2
公开(公告)日：2013-02-12
申请号：US13005264
申请日：2011-01-12
申请人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
发明人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译：集成电路相对于提供电子设备的电源电压电平提供上电复位信号。集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和第二MOS晶体管阈值电压。

5. 发明授权

US07893734B2 Power-on reset circuit 有权
标题翻译：上电复位电路
公开(公告)号：US07893734B2
公开(公告)日：2011-02-22
申请号：US12247398
申请日：2008-10-08
申请人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
发明人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译：集成电路相对于提供电子设备的电源电压电平提供上电复位信号。集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和第二MOS晶体管阈值电压。

6. 发明申请

US20090121754A1 Power-On Reset Circuit 有权
标题翻译：上电复位电路
公开(公告)号：US20090121754A1
公开(公告)日：2009-05-14
申请号：US12247398
申请日：2008-10-08
申请人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
发明人： Santiago Iriarte Garcia , Johannes Gerber , Bernhard Wolfgang Ruck
IPC分类号： H03K17/22
CPC分类号： H03K17/223 , G06F1/24 , H03K17/302 , H03K2217/0036
摘要： An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.
摘要翻译：集成电路相对于提供电子设备的电源电压电平提供上电复位信号。集成电路包括具有第一电流镜和具有第一，第二和第三串联MOS晶体管的输出级的偏置电流产生级。第二MOS晶体管和第三MOS晶体管之间的连接形成POR输出节点。第二MOS晶体管的栅极和第三MOS晶体管的栅极彼此耦合并耦合到第一电流镜。当电源电压高于第一MOS晶体管阈值时，允许通过第三MOS晶体管的电流，以及仅当电源电压大于或等于第一MOS晶体管阈值和第二MOS晶体管阈值电压。

7. 发明申请

US20090066556A1 Method and Device for Controlling a Successive Approximation Register Analog to Digital Converter 有权
标题翻译：用于控制连续近似寄存器模数转换器的方法和装置
公开(公告)号：US20090066556A1
公开(公告)日：2009-03-12
申请号：US12204301
申请日：2008-09-04
申请人： Johannes Gerber , Bernhard Wolfgang Ruck
发明人： Johannes Gerber , Bernhard Wolfgang Ruck
IPC分类号： H03M1/00
CPC分类号： H03M1/1023 , H03M1/468
摘要： A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.
摘要翻译：一种用于控制逐次逼近寄存器模数转换器的方法，包括在将电容器的第一侧连接到输入并将电容器的第二侧连接到一个电容器的采样阶段期间将电容器的第一侧连接到第一比较器输入端中间电压，采样相位将电容器的第一侧与输入端断开，并将电容器的第二侧与中间电压断开并自动调零比较器。

8. 发明申请

US20090039945A1 Bias Current Generator 有权
标题翻译：偏置电流发生器
公开(公告)号：US20090039945A1
公开(公告)日：2009-02-12
申请号：US12147048
申请日：2008-06-26
申请人： Matthias Arnold , Johannes Gerber
发明人： Matthias Arnold , Johannes Gerber
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： An electronic device generates a current with a predetermined temperature coefficient. The circuit comprises a temperature coefficient (TC) component receiving a bias current, a differential amplifier providing a buffered output voltage based on the voltage across the TC component and a resistor receiving an TC current based on the differential amplifier output voltage. The differential amplifier has a predetermined input related offset which decreases the voltage drop across the resistor. The temperature coefficient component could have either a negative temperature component (NTC) or a positive temperature component (PTC).
摘要翻译：电子装置产生具有预定温度系数的电流。电路包括接收偏置电流的温度系数（TC）分量，基于TC分量两端的电压提供缓冲输出电压的差分放大器和基于差分放大器输出电压接收TC电流的电阻器。差分放大器具有预定的输入相关偏移，其减小了电阻器两端的电压降。温度系数分量可以具有负温度分量（NTC）或正温度分量（PTC）。

9. 发明申请

US20090039845A1 METHOD AND APPARATUS FOR POWER MANAGEMENT OF A LOW DROPOUT REGULATOR 有权
标题翻译：低压差稳压器功率管理方法与装置
公开(公告)号：US20090039845A1
公开(公告)日：2009-02-12
申请号：US12168579
申请日：2008-07-07
申请人： Johannes Gerber , Matthias Arnold , Korbinian Huber
发明人： Johannes Gerber , Matthias Arnold , Korbinian Huber
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout regulator in response to said power request at a time corresponding to a start of the actual active time of the power request for an active enabled time having a duration at least the same as the actual active time and long enough to sufficiently settle the output voltage of the low dropout regulator; and disabling the low dropout regulator. In embodiments, the active enabled time is prolonged beyond the actual active time of the power request for all or at least some power requests. An electronic device includes circuits for controlling the switching of a low dropout in the described manner.
摘要翻译：切换低压差调节器的方法包括从电子设备确定功率请求的实际有效时间; 使得低压差稳压器响应于所述功率请求，在对应于具有与实际有效时间至少相同的持续时间的有效使能时间的功率请求的实际有效时间的开始的时间，并且足够长以足以稳定低压差稳压器的输出电压; 并禁用低压差稳压器。在实施例中，主动使能时间被延长超过对所有或至少一些功率请求的功率请求的实际有效时间。电子设备包括用于以所述方式控制低压差切换的电路。

10. 发明授权

US07982438B2 Method and circuit for controlling the refresh rate of sampled reference voltages 有权
标题翻译：用于控制采样参考电压刷新率的方法和电路
公开(公告)号：US07982438B2
公开(公告)日：2011-07-19
申请号：US12144996
申请日：2008-06-24
申请人： Johannes Gerber , Matthias Arnold , Korbinian Huber
发明人： Johannes Gerber , Matthias Arnold , Korbinian Huber
IPC分类号： H01M10/46
CPC分类号： G11C5/147 , G05F3/30 , G11C27/026
摘要： The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (Csamp). A comparator (COMP) compares the voltage on a first capacitor (C1) with the voltage on a second capacitor (C2). These capacitors have the capacitance of the sampling capacitor (Csamp). Upon each refresh the first capacitor (C1) samples a first voltage (Va) and the second capacitor samples a lower second voltage (Vb). The first capacitor (C1) is discharged at a first current Ia via a first leakage current source (D1). The second capacitor (C2) is discharged at a second current Ib via a second leakage current source (D2). The comparator (COMP) triggers a refresh when the voltages equal. The first current Ia is preferably an integer N times the second current Ib.
摘要翻译：本发明涉及对采样电容器（Csamp）上的参考电压的刷新率进行控制。比较器（COMP）将第一电容器（C1）上的电压与第二电容器（C2）上的电压进行比较。这些电容器具有采样电容器（Csamp）的电容。在每次刷新时，第一电容器（C1）对第一电压（Va）进行采样，而第二电容器采样较低的第二电压（Vb）。第一电容器（C1）经由第一漏电流源（D1）以第一电流Ia放电。第二电容器（C2）经由第二漏电流源（D2）在第二电流Ib放电。当电压相等时，比较器（COMP）触发刷新。第一电流Ia优选为第二电流Ib的整数N倍。

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