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1. 发明申请

US20120204016A1 Rewriting Branch Instructions Using Branch Stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US20120204016A1
公开(公告)日：2012-08-09
申请号：US13443188
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/318
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

2. 发明申请

US20120198170A1 Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction 有权
标题翻译：动态重写缓存线驱逐响应中的分支指令
公开(公告)号：US20120198170A1
公开(公告)日：2012-08-02
申请号：US13444890
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3806 , G06F12/0875 , G06F12/12
摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.
摘要翻译：提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。确定当前高速缓存行是否将从指令高速缓存中逐出。处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

3. 发明申请

US20110219222A1 Building Approximate Data Dependences with a Moving Window 失效
标题翻译：用移动窗口构建近似数据依赖
公开(公告)号：US20110219222A1
公开(公告)日：2011-09-08
申请号：US12717985
申请日：2010-03-05
申请人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Kai-Ting A. Wang , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Kai-Ting A. Wang , Xiaotong Zhuang
IPC分类号： G06F9/32
CPC分类号： G06F9/32
摘要： Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a portion of code. The mechanisms receive a memory access of an iteration of the portion of code, the memory access having an address for access the memory and an access type indicating at least one of a read or a write access type. An entry in a moving look-back window data structure is generated corresponding to a memory location accessed by the memory access. The entry comprises at least an identification of the address, the access type, and an iteration number corresponding to the iteration of the memory access. The moving look-back window data structure is utilized to determine dependence information for memory accesses over a plurality of iterations of the portion of code.
摘要翻译：提供了使用移动后视窗构建近似数据依赖关系的机制。机制跟踪代码的一部分执行迭代的存储器访问的依赖信息。机构接收代码部分的迭代的存储器访问，存储器访问具有用于访问存储器的地址和指示读取或写入访问类型中的至少一个的访问类型。对应于由存储器访问访问的存储器位置产生移动后视窗数据结构中的条目。该条目至少包括对应于存储器访问的迭代的地址的标识，访问类型和迭代号。移动后视窗数据结构用于确定代码部分的多个迭代中的存储器访问的依赖信息。

4. 发明申请

US20140068581A1 OPTIMIZED DIVISION OF WORK AMONG PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM 审中-公开
标题翻译：异构加工系统中处理器的优化工作部分
公开(公告)号：US20140068581A1
公开(公告)日：2014-03-06
申请号：US13598780
申请日：2012-08-30
申请人： Tong Chen , John K.P. O'Brien , Zehra N. Sura
发明人： Tong Chen , John K.P. O'Brien , Zehra N. Sura
IPC分类号： G06F9/45
CPC分类号： G06F8/451
摘要： A compiler implemented by a computer performs optimized division of work across heterogeneous processors. The compiler divides source code into code sections and characterizes each of the code sections based on pre-defined criteria. Each of the code sections is characterized as at least one of: allocate to a main processor, allocate to a processing element, allocate to one of a parameterized main processor and a parameterized processing element, and indeterminate. The compiler analyzes side-effects and costs of executing the code sections on allocated processors, and transforms the code sections based on results of the analyzing. The transforming includes re-characterizing the code sections for alternate execution in a runtime environment.
摘要翻译：由计算机实现的编译器在异构处理器之间执行优化的分工。编译器将源代码分为代码段，并根据预定义的标准来表征每个代码段。每个代码段被表征为以下至少一个：分配给主处理器，分配给处理元件，分配给参数化主处理器和参数化处理元件中的一个，并且不确定。编译器分析在分配的处理器上执行代码段的副作用和成本，并根据分析结果转换代码段。转换包括重新表征代码段，以便在运行时环境中进行备用执行。

5. 发明申请

US20110321021A1 Arranging Binary Code Based on Call Graph Partitioning 有权
标题翻译：基于调用图划分二进制代码
公开(公告)号：US20110321021A1
公开(公告)日：2011-12-29
申请号：US12823244
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
摘要翻译：提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。这些机制产生一部分代码的调用图。调用图中的节点和边被加权以生成加权调用图。然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码调用图被组合到基于分区的各个高速缓存行。然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

6. 发明申请

US20110321002A1 Rewriting Branch Instructions Using Branch Stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US20110321002A1
公开(公告)日：2011-12-29
申请号：US12823204
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

7. 发明申请

US20110055484A1 Detecting Task Complete Dependencies Using Underlying Speculative Multi-Threading Hardware 有权
标题翻译：使用基础投机多线程硬件检测任务完成依赖关系
公开(公告)号：US20110055484A1
公开(公告)日：2011-03-03
申请号：US12553314
申请日：2009-09-03
申请人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/3814 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3859
摘要： Mechanisms are provided for tracking dependencies of threads in a multi-threaded computer program execution. The mechanisms detect a dependency of a first thread's execution on results of a second thread's execution in an execution flow of the multi-threaded computer program. The mechanisms further store, in a hardware thread dependency vector storage associated with the first thread's execution, an identifier of the dependency by setting at least one bit in the hardware thread dependency vector storage corresponding to the second thread. Moreover, the mechanisms schedule tasks performed by the multi-threaded computer program based on the hardware thread dependency vector storage to minimize squashing of threads.
摘要翻译：提供了用于跟踪多线程计算机程序执行中线程依赖性的机制。该机制检测第一个线程执行对多线程计算机程序执行流程中第二个线程执行结果的依赖性。这些机制通过在与第二线程相对应的硬件线程相关性向量存储中设置至少一个比特来进一步存储与第一线程的执行相关联的硬件线程依赖向量存储中的依赖关系的标识符。此外，该机制基于硬件线程依赖向量存储来调度由多线程计算机程序执行的任务以最小化线程的挤压。

8. 发明申请

US20140068582A1 OPTIMIZED DIVISION OF WORK AMONG PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM 审中-公开
公开(公告)号：US20140068582A1
公开(公告)日：2014-03-06
申请号：US13608043
申请日：2012-09-10
申请人： Tong Chen , John K.P. O'Brien , Zehra N. Sura
发明人： Tong Chen , John K.P. O'Brien , Zehra N. Sura
IPC分类号： G06F9/45
CPC分类号： G06F8/451
摘要： A compiler implemented by a computer performs optimized division of work across heterogeneous processors. The compiler divides source code into code sections and characterizes each of the code sections based on pre-defined criteria. Each of the code sections is characterized as at least one of: allocate to a main processor, allocate to a processing element, allocate to one of a parameterized main processor and a parameterized processing element, and indeterminate. The compiler analyzes side-effects and costs of executing the code sections on allocated processors, and transforms the code sections based on results of the analyzing. The transforming includes re-characterizing the code sections for alternate execution in a runtime environment.

9. 发明申请

US20110320785A1 Binary Rewriting in Software Instruction Cache 有权
标题翻译：软件指令缓存中的二进制重写
公开(公告)号：US20110320785A1
公开(公告)日：2011-12-29
申请号：US12823194
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/38 , G06F12/08 , G06F9/318
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译：提供了用于在代码的一部分中动态地重写分支指令的机制。这些机制在代码的一部分中执行分支指令。这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，机制将代码部分的执行重定向到指令高速缓存运行时系统。

10. 发明申请

US20090083702A1 System and Method for Selective Code Generation Optimization for an Advanced Dual-Representation Polyhedral Loop Transformation Framework 失效
标题翻译：用于高级双表示多面体环转换框架的选择性代码生成优化的系统和方法
公开(公告)号：US20090083702A1
公开(公告)日：2009-03-26
申请号：US11861493
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K.P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/44
CPC分类号： G06F8/4452
摘要： A system and method for selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization.
摘要翻译：提供了一种用于高级双表示多面体环转换框架的选择性代码生成优化的系统和方法。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。

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