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1. 发明申请

US20210126523A1 ELECTRIC POWER CONVERSION SYSTEM 有权
公开(公告)号：US20210126523A1
公开(公告)日：2021-04-29
申请号：US17139781
申请日：2020-12-31
申请人： Tong Chen
发明人： Tong Chen
IPC分类号： H02M1/32 , G08B21/02 , G01R31/52
摘要： Disclosed is a power conversion system for notifying electrical faults and protection against electrical shocks. The power conversion system includes a first circuit having a primary winding; a second circuit having a secondary winding, and a core, wherein the primary winding and the secondary winding are coiled around the core. The power conversion system further includes an impedance and a detection module in series bridged to the first circuit and the second circuit forming the third circuit. The detection module is configured to detect any fault electrical current flowing from the first circuit to the second circuit via the third circuit. The detection module is connected to an alert unit for indicating the presence of fault current in the third circuit and optionally the detector module may also connect to a circuit breaker.

2. 发明授权

US09506823B2 Bonding stress testing arrangement and method of determining stress 有权
标题翻译：粘结应力测试方法和应力测定方法
公开(公告)号：US09506823B2
公开(公告)日：2016-11-29
申请号：US13696432
申请日：2011-05-03
申请人： Cheryl Sharmani Selvanayagam , Xiaowu Zhang , Tai Chong Chai , Alastair David Trigg , Cheng Kuo Cheng , Xian Tong Chen , Kripesh Vaidyanathan
发明人： Cheryl Sharmani Selvanayagam , Xiaowu Zhang , Tai Chong Chai , Alastair David Trigg , Cheng Kuo Cheng , Xian Tong Chen , Kripesh Vaidyanathan
IPC分类号： G01L1/22 , H01L21/66
CPC分类号： G01L1/22 , H01L22/12 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A bonding stress testing arrangement and a method of determining stress are provided. The bonding stress testing arrangement includes at least one bond pad; a sensor assembly comprising any one of a first sensor arrangement, a second sensor arrangement and a combination of the first sensor arrangement and the second sensor arrangement; wherein the first sensor arrangement is adapted to measure an average stress on a portion of a bonding area under the at least one bond pad, and the second sensor arrangement is adapted to determine stress distribution over a portion or an entire of the bonding area under the at least one bond pad.
摘要翻译：提供接合应力测试装置和确定应力的方法。接合应力测试装置包括至少一个接合焊盘; 传感器组件，包括第一传感器布置，第二传感器布置以及第一传感器布置和第二传感器布置的组合中的任一个; 其中所述第一传感器装置适于测量所述至少一个接合焊盘下方的接合区域的一部分上的平均应力，并且所述第二传感器装置适于确定在所述至少一个接合焊盘下方的部分或整个所述接合区域的应力分布至少一个键盘。

3. 发明授权

US09459851B2 Arranging binary code based on call graph partitioning 有权
标题翻译：基于调用图分区来排列二进制代码
公开(公告)号：US09459851B2
公开(公告)日：2016-10-04
申请号：US12823244
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
摘要翻译：提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。这些机制产生一部分代码的调用图。调用图中的节点和边被加权以生成加权调用图。然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码调用图被组合到基于分区的各个高速缓存行。然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

4. 发明授权

US08846627B2 Method for treatment of malaria 有权
标题翻译：治疗疟疾的方法
公开(公告)号：US08846627B2
公开(公告)日：2014-09-30
申请号：US13452962
申请日：2012-04-23
申请人： Weidong Zhang , Jin Huang , Lei Shan , Honglin Li , Liyan Wang , Shoude Zhang , Weiqiang Lu , Juan Su , Tong Chen
发明人： Weidong Zhang , Jin Huang , Lei Shan , Honglin Li , Liyan Wang , Shoude Zhang , Weiqiang Lu , Juan Su , Tong Chen
IPC分类号： A61K31/70 , A61K31/7048
CPC分类号： A61K31/7048 , Y02A50/411
摘要： A method for treatment of malaria including administering to a patient in need thereof a flavonoid glycoside compound.
摘要翻译：一种治疗疟疾的方法，包括向有需要的患者施用类黄酮糖苷化合物。

5. 发明授权

US08836439B2 Dynamic frequency tuning of electric and magnetic metamaterial response 有权
标题翻译：电磁特性响应的动态频率调谐
公开(公告)号：US08836439B2
公开(公告)日：2014-09-16
申请号：US11871642
申请日：2007-10-12
申请人： John F. O'Hara , Richard Averitt , Willie Padilla , Hou-Tong Chen
发明人： John F. O'Hara , Richard Averitt , Willie Padilla , Hou-Tong Chen
IPC分类号： H01P7/08 , H01Q15/00 , H03J1/00 , H03C7/02
CPC分类号： H01P7/08 , H01Q15/0086 , H03C7/02 , H03J1/00
摘要： A geometrically modifiable resonator is comprised of a resonator disposed on a substrate, and a means for geometrically modifying the resonator. The geometrically modifiable resonator can achieve active optical and/or electronic control of the frequency response in metamaterials and/or frequency selective surfaces, potentially with sub-picosecond response times. Additionally, the methods taught here can be applied to discrete geometrically modifiable circuit components such as inductors and capacitors. Principally, controlled conductivity regions, using either reversible photodoping or voltage induced depletion activation, are used to modify the geometries of circuit components, thus allowing frequency tuning of resonators without otherwise affecting the bulk substrate electrical properties. The concept is valid over any frequency range in which metamaterials are designed to operate.
摘要翻译：几何可修改的谐振器由设置在基板上的谐振器和用于几何校正谐振器的装置组成。几何可修改的谐振器可以实现对超材料和/或频率选择表面的频率响应的有源光学和/或电子控制，潜在地具有次皮秒响应时间。另外，这里教导的方法可以应用于离散几何可修改的电路部件，如电感器和电容器。主要地，使用可逆光电二极管或电压诱导耗尽激活的受控导电区域用于修改电路部件的几何形状，从而允许谐振器的频率调谐，而不影响体衬底的电性能。该概念在超材料设计运行的任何频率范围内均有效。

6. 发明授权

US08656142B2 Managing multiple speculative assist threads at differing cache levels 失效
标题翻译：管理不同缓存级别的多个投机辅助线程
公开(公告)号：US08656142B2
公开(公告)日：2014-02-18
申请号：US12903620
申请日：2010-10-13
申请人： Tong Chen , Yaoqing Gao
发明人： Tong Chen , Yaoqing Gao
IPC分类号： G06F9/30
CPC分类号： G06F12/0862
摘要： An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a command from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive to receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from the second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by the memory, to the second processor into a target cache level on the second processor.
摘要翻译：示例性实施例提供了一种用于管理用于数据预取的多个推测辅助线程的计算机实现的过程，其将命令从第一处理器的辅助线程发送到第二处理器和存储器，其中该命令的参数指定处理器标识符第二处理器，响应于接收到所述命令，响应于接收到指示提供所述高速缓存行的能力的由所述存储器回复的命令，所述第二处理器的指示接收作为所述预取的目标的高速缓存行的能力，响应于从所述第二处理器和所述存储器接收到的答复，由所述第一处理器发送对所述第二处理器和所述存储器的组合响应，其中所述组合响应指示动作，并且响应于所述动作指示事务可以继续发送所述存储器将所请求的高速缓存行提供给所述第二处理器到所述第二处理器上的目标高速缓存级别。

7. 发明授权

US08561044B2 Optimized code generation targeting a high locality software cache 失效
标题翻译：针对高位置软件缓存的优化代码生成
公开(公告)号：US08561044B2
公开(公告)日：2013-10-15
申请号：US12246602
申请日：2008-10-07
申请人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references. Transforming of the original computer code comprises inserting, into the original computer code, instructions to execute initialization, lookup, and cleanup operations associated with the leading memory reference and trailing memory reference in a different manner from initialization, lookup, and cleanup operations for the one or more middle memory references.
摘要翻译：提供了针对高位置软件缓存的优化代码生成机制。解析原始计算机代码以识别原始计算机代码中的内存引用。内存引用被分类为常规内存引用或不规则内存引用。常规内存引用由高位置缓存机制控制。原始计算机代码由编译器转换以生成转换的计算机代码，其中常规存储器引用被分组成一个或多个存储器参考流，每个存储器参考流具有前导存储器引用，尾随存储器引用和一个或多个中间内存引用。原始计算机代码的转换包括将原始计算机代码中的指令以不同于初始化，查找和清除操作的方式与前导存储器引用和尾随存储器引用相关联的执行初始化，查找和清除操作的指令进行插入或更多的中间内存引用。

8. 发明授权

US08522225B2 Rewriting branch instructions using branch stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US08522225B2
公开(公告)日：2013-08-27
申请号：US12823204
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

9. 发明申请

US20120265941A1 Prefetching Irregular Data References for Software Controlled Caches 失效
标题翻译：预取软件控制缓存的不规则数据引用
公开(公告)号：US20120265941A1
公开(公告)日：2012-10-18
申请号：US13534794
申请日：2012-06-27
申请人： Tong Chen , Marc Gonzelez allada , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Marc Gonzelez allada , Zehra N. Sura , Tao Zhang
IPC分类号： G06F12/08
CPC分类号： G06F8/4442
摘要： Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.
摘要翻译：提供了将不规则内存引用预取到软件控制的缓存中。编译器分析源代码以识别包含不规则存储器引用的多个循环中的至少一个循环。编译器确定至少一个循环内的不规则存储器引用是否是优化的候选者。响应于可以优化不规则存储器引用的指示，编译器确定不规则存储器引用是否对预取有效。响应于不规则存储器引用对于预取有效的指示，将不规则存储器引用的地址的存储语句插入到至少一个循环中。运行时库调用插入到不规则内存引用的预取运行时库中。当调用运行时库调用时，与不规则内存引用相关联的数据将被预取到软件控制的缓存中。

10. 发明申请

US20120204016A1 Rewriting Branch Instructions Using Branch Stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US20120204016A1
公开(公告)日：2012-08-09
申请号：US13443188
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/318
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

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