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1. 发明申请

US20110207315A1 METHOD OF FABRICATING GATE STRUCTURES 有权
标题翻译：制造门结构的方法
公开(公告)号：US20110207315A1
公开(公告)日：2011-08-25
申请号：US12708586
申请日：2010-02-19
申请人： Pochi WU , Ju-Wang Hsu , Ryan Chia-Jen Chen
发明人： Pochi WU , Ju-Wang Hsu , Ryan Chia-Jen Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/32137 , H01L21/28194 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl2. The first dummy gate electrode is removed in a second plasma environment comprising NF3, HBr, and Cl2 thereby leaving a hole surrounded by the first spacers. The hole is filled with a metal gate layer.
摘要翻译：本公开的实施例包括形成金属栅极结构的方法。提供基板。第一虚拟栅电极和第二虚拟栅电极形成在基板上。第一虚拟栅极电极在其侧壁上包括第一间隔物，第二伪栅电极在其侧壁上包括第二间隔物。形成硬掩模层以覆盖第一伪栅极电极和第二虚拟栅极电极。在硬掩模层上的图案化的光刻胶层，其覆盖在第二伪栅电极上的硬掩模层的一部分，并且将暴露的第一伪栅电极的硬掩模层的一部分留下。去除第一伪栅电极上的暴露的硬掩模层的部分。第一间隔物和第一伪栅电极暴露于包含O 2，HBr和Cl 2的第一等离子体环境中。在包括NF 3，HBr和Cl 2的第二等离子体环境中去除第一伪栅电极，从而留下被第一间隔物包围的孔。该孔填充有金属栅极层。

2. 发明授权

US07875547B2 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US07875547B2
公开(公告)日：2011-01-25
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

3. 发明授权

US07678655B2 Spacer layer etch method providing enhanced microelectronic device performance 有权
标题翻译：间隔层蚀刻方法提供增强的微电子器件性能
公开(公告)号：US07678655B2
公开(公告)日：2010-03-16
申请号：US11495348
申请日：2006-07-28
申请人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
发明人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6653
摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.
摘要翻译：用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

4. 发明授权

US07256498B2 Resistance-reduced semiconductor device and methods for fabricating the same 有权
标题翻译：电阻降低半导体器件及其制造方法
公开(公告)号：US07256498B2
公开(公告)日：2007-08-14
申请号：US11190913
申请日：2005-07-28
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L27/04
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659
摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.
摘要翻译：半导体器件及其制造方法。半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。具有导电接触的第一介电层覆盖电阻减小的晶体管。具有第一导电特征的第二介电层覆盖在第一介电层上。具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

5. 发明授权

US07256137B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US07256137B2
公开(公告)日：2007-08-14
申请号：US11052938
申请日：2005-02-07
申请人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
发明人： Chii-Ming Wu , Chih-Wei Chang , Shau-Lin Shue , Ju-Wang Hsu , Ming-Huan Tsai
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

6. 发明授权

US07223647B2 Method for forming integrated advanced semiconductor device using sacrificial stress layer 有权
标题翻译：使用牺牲应力层形成集成先进半导体器件的方法
公开(公告)号：US07223647B2
公开(公告)日：2007-05-29
申请号：US10981925
申请日：2004-11-05
申请人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
发明人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L21/823878 , H01L29/7843 , Y10S438/938
摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.
摘要翻译：用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。应力膜可以是拉伸或压缩氮化物膜。在硅化物形成工艺之前进行退火处理。在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

7. 发明申请

US20060183279A1 METHOD FOR SELECTIVELY STRESSING MOSFETS TO IMPROVE CHARGE CARRIER MOBILITY 审中-公开
标题翻译：选择性地压力MOSFET以提高电荷载流子迁移率的方法
公开(公告)号：US20060183279A1
公开(公告)日：2006-08-17
申请号：US11279016
申请日：2006-04-07
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

8. 发明申请

US20060180854A1 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US20060180854A1
公开(公告)日：2006-08-17
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
IPC分类号： H01L31/113
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

9. 发明授权

US07052946B2 Method for selectively stressing MOSFETs to improve charge carrier mobility 有权
公开(公告)号：US07052946B2
公开(公告)日：2006-05-30
申请号：US10798960
申请日：2004-03-10
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

10. 发明申请

US20060014396A1 Method for forming a resist protect layer 有权
标题翻译：形成抗蚀剂保护层的方法
公开(公告)号：US20060014396A1
公开(公告)日：2006-01-19
申请号：US10892014
申请日：2004-07-14
申请人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/31111 , H01L21/823481 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.
摘要翻译：在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。在半导体衬底上形成隔离结构。在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。形成光致抗蚀剂掩模以部分覆盖原始氮化物层。执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

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