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1. 发明授权

US08614132B2 Integrated circuit device with well controlled surface proximity and method of manufacturing same 有权
标题翻译：具有良好控制的表面接近的集成电路器件及其制造方法
公开(公告)号：US08614132B2
公开(公告)日：2013-12-24
申请号：US13240025
申请日：2011-09-22
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

2. 发明授权

US07510940B2 Method for fabricating dual-gate semiconductor device 有权
标题翻译：双栅半导体器件制造方法
公开(公告)号：US07510940B2
公开(公告)日：2009-03-31
申请号：US11707490
申请日：2007-02-16
申请人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
发明人： Chen-Nan Yeh , Mong Song Liang , Ryan Chia-Jen Chen , Yuan-Hung Chiu
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.
摘要翻译：一种制造双栅极半导体器件的方法。优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料，蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。

3. 发明授权

US07390753B2 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US07390753B2
公开(公告)日：2008-06-24
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

4. 发明申请

US20070111110A1 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US20070111110A1
公开(公告)日：2007-05-17
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： G03F1/00 , C03C15/00 , G03C5/00
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

5. 发明授权

US07060628B2 Method for fabricating a hard mask polysilicon gate 有权
标题翻译：硬掩模多晶硅栅极的制造方法
公开(公告)号：US07060628B2
公开(公告)日：2006-06-13
申请号：US10804449
申请日：2004-03-19
申请人： Ming-Jie Huang , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ming-Jie Huang , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon layer according to the pattern of the hard mask layer using a fluorine-containing etchant gas. The resulting sidewall profile of the etched polysilicon layer is substantially straight, uniform and devoid of a necking or notched configuration.
摘要翻译：公开了一种用于形成图案化的含硅层的方法。该方法包括提供衬底，在衬底上提供多晶硅层，在多晶硅层上提供硬掩模层，图案化和蚀刻硬掩模层，并根据硬掩模层的图案使用氟 - 含有蚀刻剂气体。蚀刻的多晶硅层的所得到的侧壁轮廓基本上是直的，均匀的且没有颈缩或缺口构型。

6. 发明申请

US20060046323A1 In-situ critical dimension measrument 有权
标题翻译：原位关键维度测量
公开(公告)号：US20060046323A1
公开(公告)日：2006-03-02
申请号：US11053300
申请日：2005-02-07
申请人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
发明人： Shiang-Bau Wang , Yuan-Hung Chiu , Hun-Jan Tao , Chao-Tzung Tsai
IPC分类号： H01L21/66
CPC分类号： H01L22/20
摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.
摘要翻译：提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

7. 发明申请

US20050136680A1 Plasma treatment and etching process for ultra-thin dielectric films 失效
标题翻译：超薄电介质膜的等离子体处理和蚀刻工艺
公开(公告)号：US20050136680A1
公开(公告)日：2005-06-23
申请号：US10738237
申请日：2003-12-17
申请人： Ju-Wang Hsu , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/311 , H01L21/314 , H01L21/336 , H01L21/768 , H01L21/3205 , H01L21/461 , H01L21/31
CPC分类号： H01L21/0234 , H01L21/0214 , H01L21/0217 , H01L21/02323 , H01L21/31116 , H01L21/3143 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L29/6653 , H01L29/6656
摘要： A method for dry etching a dielectric layer including providing a substrate; forming at least one overlying dielectric layer over the substrate; subjecting the at least one overlying layer to a plasma oxidizing process; and, subjecting the at least one overlying layer to a plasma etching process.
摘要翻译：一种用于干蚀刻包括提供衬底的电介质层的方法; 在所述衬底上形成至少一个覆盖介质层; 对所述至少一个上覆层进行等离子体氧化处理; 以及对所述至少一个上覆层进行等离子体蚀刻工艺。

8. 发明申请

US20050092348A1 Method for cleaning an integrated circuit device using an aqueous cleaning composition 审中-公开
标题翻译：使用水性清洁组合物清洁集成电路装置的方法
公开(公告)号：US20050092348A1
公开(公告)日：2005-05-05
申请号：US10701708
申请日：2003-11-05
申请人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ju-Chien Chiang , Ming-Huan Tsai , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： B08B3/08 , B08B3/12 , C11D3/39 , C11D7/08 , C11D11/00 , H01L21/306 , H01L21/311
CPC分类号： H01L21/02052 , B08B3/08 , B08B3/12 , C11D3/3947 , C11D7/08 , C11D11/0047 , H01L21/31122
摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.
摘要翻译：本发明提供用于清洁集成电路基板的水性组合物。具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括（a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

9. 发明申请

US20050081781A1 Fully dry, Si recess free process for removing high k dielectric layer 审中-公开
标题翻译：完全干燥，Si无凹槽工艺，用于去除高k电介质层
公开(公告)号：US20050081781A1
公开(公告)日：2005-04-21
申请号：US10688045
申请日：2003-10-17
申请人： Huan-Just Lin , Ming-Huan Tsai , Li-Te Lin , Yuan-Hung Chiu , Han-Jan Tao
发明人： Huan-Just Lin , Ming-Huan Tsai , Li-Te Lin , Yuan-Hung Chiu , Han-Jan Tao
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/28 , H01L21/311 , H01L21/316 , H01L29/49 , H01L29/51
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L21/28194 , H01L21/31122 , H01L21/31645 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.
摘要翻译：描述了用于从衬底去除高k电介质层而不损坏衬底并且相对于栅极层具有高选择性的全干蚀刻方法。蚀刻由BCl 3 3，碳氟化合物和惰性气体组成。低RF偏置功率是优选的。该方法也可以用于去除衬底和高k电介质层之间的界面层。实现了每分钟55埃的HfO 2/2蚀刻速率，而不会在硅衬底中产生凹陷，并且对多晶硅的蚀刻选择性大于10:1。该方法也提供更好的STI氧化物控制。通过高k介电层的蚀刻可以在与蚀刻工艺相同的蚀刻室中进行以形成栅电极。

10. 发明授权

US06849531B1 Phosphoric acid free process for polysilicon gate definition 失效
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US06849531B1
公开(公告)日：2005-02-01
申请号：US10718876
申请日：2003-11-21
申请人： Li-Te S. Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a gate structure for a MOSFET device featuring the employment of dual anti-reflective coating (ARC) layers to enhance gate structure resolution, and featuring a dry procedure for removal of all ARC layers avoiding the use of hot phosphoric acid, has been developed. After formation of a polysilicon layer on an underlying silicon dioxide gate insulator layer, a capping silicon oxide, a dielectric ARC layer, and an overlying organic ARC layer are deposited. A photoresist shape is formed and used as an etch mask to allow a first anisotropic RIE procedure to define the desired gate structure shape in the dual ARC layers and in the capping silicon oxide layer. After removal of the photoresist shape and the overlying organic ARC layer a second anisotropic RIE procedure is used to define a desired polysilicon gate structure, with the second anisotropic RIE procedure also resulting in the removal of the dielectric ARC shape. A final hydrofluoric acid type solution is then used to remove the capping silicon oxide shape as well as to remove the portions of the silicon dioxide gate insulator layer not covered by the polysilicon gate structure.
摘要翻译：一种限定用于MOSFET器件的栅极结构的方法，其特征在于采用双抗反射涂层（ARC）层以增强栅极结构分辨率，并且具有用于去除所有ARC层的干法以避免使用热磷酸，具有已经开发在下面的二氧化硅栅极绝缘体层上形成多晶硅层之后，沉积覆盖氧化硅，电介质ARC层和上覆的有机ARC层。形成光致抗蚀剂形状并用作蚀刻掩模，以允许第一各向异性RIE程序在双ARC层和封盖氧化硅层中限定所需的栅极结构形状。在除去光致抗蚀剂形状和上覆的有机ARC层之后，使用第二各向异性RIE程序来限定期望的多晶硅栅极结构，其中第二各向异性RIE程序也导致去除电介质ARC形状。然后使用最终的氢氟酸型溶液去除封端氧化硅形状以及去除未被多晶硅栅极结构覆盖的二氧化硅栅极绝缘体层的部分。

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