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1. 发明申请

US20180331690A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER COMBINED WITH FLASH ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20180331690A1
公开(公告)日：2018-11-15
申请号：US15976708
申请日：2018-05-10
申请人： UNIST (Ulsan National Institute of Science and Technology)
发明人： Jae Joon KIM , Kyeong Hwan PARK
IPC分类号： H03M1/46 , H03M7/16 , H03M1/36
CPC分类号： H03M1/462 , H03M1/145 , H03M1/361 , H03M1/365 , H03M1/466 , H03M1/68 , H03M7/165
摘要： An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.

2. 发明申请

US20180309460A1 POWER-EFFICIENT FLASH QUANTIZER FOR DELTA SIGMA CONVERTER 审中-公开
公开(公告)号：US20180309460A1
公开(公告)日：2018-10-25
申请号：US15914833
申请日：2018-03-07
申请人： Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
发明人： Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
IPC分类号： H03M3/00 , H03M1/06 , H03M1/36 , H03M3/02 , H03M3/04
CPC分类号： H03M3/424 , H03M1/002 , H03M1/066 , H03M1/361 , H03M1/365 , H03M3/02 , H03M3/04 , H03M3/32 , H03M3/452 , H03M3/464
摘要： A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

3. 发明授权

US09983304B2 Delta-sigma digital radiometric system 有权
公开(公告)号：US09983304B2
公开(公告)日：2018-05-29
申请号：US14627094
申请日：2015-02-20
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： Andrew D. Smith , Leland Gilreath , Khanh Thai
IPC分类号： G01S3/02 , G01S13/89 , H03M1/48 , H03M1/18 , H03M1/20 , H03M1/36
CPC分类号： G01S13/89 , H03M1/182 , H03M1/20 , H03M1/365 , H03M1/48
摘要： A passive radiometric system for thermally imaging objects in a scene. The system includes a digital square-law quantizer circuit including a plurality of comparators and a voltage divider network having a plurality of resistors. Each comparator receives a different reference signal generated by the voltage divider network and a common power signal from an antenna and outputs a high or low digital bit signal. The system also includes a delta-sigma circuit having a weighting table responsive to the digital bit signals from the comparators that converts the digital bit signals to a normalized bit word. The delta-sigma circuit also includes an accumulator that receives the digital bit words from the weighting table and provides an average of the digital bit words. The system also includes a digital-to-analog converter that converts the averaged bit words to an analog signal that is provided as a feedback signal to the quantizer circuit.

4. 发明申请

US20180091166A1 RADIO FREQUENCY FLASH ADC CIRCUITS 审中-公开
公开(公告)号：US20180091166A1
公开(公告)日：2018-03-29
申请号：US15830144
申请日：2017-12-04
申请人： Maxlinear Asia Singapore PTE LTD
发明人： William Michael LYE , Anthony Eugene ZORTEA , Jatinder CHANA
IPC分类号： H03M1/12 , H03M1/20 , H03K5/24 , H03M1/10 , H03M1/36
CPC分类号： H03M1/1245 , H03K5/249 , H03M1/1023 , H03M1/204 , H03M1/365
摘要： A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

5. 发明申请

US20170294918A1 Electronic Switching and Protection Circuit 审中-公开
公开(公告)号：US20170294918A1
公开(公告)日：2017-10-12
申请号：US15094463
申请日：2016-04-08
申请人： Infineon Technologies AG
发明人： Robert Illing , Christian Djelassi , Markus Ladurner , David Jansson
IPC分类号： H03M1/12 , H02H3/38
CPC分类号： H03M1/124 , H02H3/087 , H02H3/0935 , H02H3/10 , H02H3/202 , H02H3/38 , H02H5/041 , H03M1/365
摘要： An embodiment electronic circuit includes an electronic switch comprising a load path, a first protection circuit configured to generate a first protection signal based on a current-time-characteristic of a load current through the load path of the electronic switch, and a drive circuit configured to drive the electronic switch based on the first protection signal. The first protection circuit includes an analog-to-digital converter (ADC) configured to receive an ADC input signal representing the load current, to sample the ADC input signal once in each of a plurality of successive sampling periods, and to output an ADC output signal that includes a sequence of values such that each of the values represents a respective sample of the ADC input signal. The ADC is configured to pseudo-randomly select a sample time in each sampling period.

6. 发明授权

US09722647B2 Calibration techniques for sigma delta transceivers 有权
公开(公告)号：US09722647B2
公开(公告)日：2017-08-01
申请号：US15433991
申请日：2017-02-15
申请人： GM GLOBAL TECHNOLOGY OPERATIONS LLC
发明人： Timothy J. Talty , Mohiuddin Ahmed , Cynthia D. Baringer , Yen-Cheng Kuan , James Chingwei Li , Hsuanyu Pan , Emilio A. Sovero
IPC分类号： H04B1/04 , H04B1/40
CPC分类号： H04B1/0475 , H03F3/24 , H03M1/0673 , H03M1/365 , H03M1/662 , H03M3/408 , H03M3/424 , H04B1/0007 , H04B1/1036 , H04B1/3822 , H04B1/40 , H04B2001/0408 , H04B2001/0425 , H04B2001/1063 , H04L1/0071
摘要： A cellular radio architecture that includes a transceiver front-end circuit including an antenna and a switch module having a switching network that directs analog transmit signals to be transmitted to the antenna and receives receive signals from the antenna. The architecture further includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer module, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture also includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to the transmit signals. The transmitter module includes a tunable bandpass filter and a power amplifier for amplifying the transmit signals before transmitting. The architecture also includes a calibration feedback and switch module that receives the amplified signals from the power amplifier.

7. 发明授权

US09698855B1 Performance optimization of power scaled delta sigma modulators using a reconfigurable gm-array 有权
公开(公告)号：US09698855B1
公开(公告)日：2017-07-04
申请号：US15433928
申请日：2017-02-15
申请人： GM GLOBAL TECHNOLOGY OPERATIONS LLC
发明人： Timothy J. Talty , Cynthia D. Baringer , Mohiuddin Ahmed , James Chingwei Li , Yen-Cheng Kuan , Hsuanyu Pan , Emilio A. Sovero
IPC分类号： H04B1/40 , H04B1/3822
CPC分类号： H04B1/0475 , H03F3/24 , H03M1/0673 , H03M1/365 , H03M1/662 , H03M3/408 , H03M3/424 , H04B1/0007 , H04B1/1036 , H04B1/3822 , H04B1/40 , H04B2001/0408 , H04B2001/0425 , H04B2001/1063 , H04L1/0071
摘要： A cellular radio architecture that includes a receiver module having a delta-sigma modulator that includes a plurality of gm cells configured in stages, where each stage includes at least two gm cells and an LC filter circuit. The gm cells in each stage can be controlled to be active or inactive to convert, for example, the modulator from a fourth order modulator to a second order modulator to reduce power dissipation. Further, the gm cells can be controlled to optimize a dynamic range of the modulator and to redirect current from inactive cells to active cells in order to optimize power consumption.

8. 发明授权

US09467160B2 Flash ADC with interpolators 有权
标题翻译：带内插器的闪存ADC
公开(公告)号：US09467160B2
公开(公告)日：2016-10-11
申请号：US14538013
申请日：2014-11-11
申请人： MediaTek Inc.
发明人： Wen-Hua Chang
IPC分类号： H03M1/12 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An ADC is provided. The ADC includes a plurality of pre-amplifiers, dynamic comparators coupled to the pre-amplifiers, interpolators and an encoder. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog signals and a first reference voltage and a second reference voltage different from the first reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier. Each interpolator provides an interpolating signal according to the first and second comparing signals of two of the dynamic comparators. The encoder provides a digital output according to the interpolating signals. The first and second comparing signals are the same in a reset phase, and the first and second comparing signals are complementary according to the pair of differential outputs of the corresponding pre-amplifier in an evaluation phase.
摘要翻译：提供了一个ADC。 ADC包括多个预放大器，耦合到前置放大器，内插器和编码器的动态比较器。每个前置放大器根据一对差分模拟信号和不同于第一参考电压的第一参考电压和第二参考电压提供一对差分输出。每个动态比较器根据相应的前置放大器的差分输出对提供第一比较信号和第二比较信号。每个内插器根据两个动态比较器的第一和第二比较信号提供内插信号。编码器根据内插信号提供数字输出。第一和第二比较信号在复位阶段相同，并且第一和第二比较信号根据评估阶段中对应的前置放大器的差分输出的对而互补。

9. 发明申请

US20160169947A1 Measurement Circuit 审中-公开
标题翻译：测量电路
公开(公告)号：US20160169947A1
公开(公告)日：2016-06-16
申请号：US14964659
申请日：2015-12-10
申请人： Dialog Semiconductor (UK) Limited
发明人： Michele De Fazio , Andrea Acquas , Fabio Rigoni
IPC分类号： G01R19/30 , H03K5/24 , G01R19/10
CPC分类号： G01R19/30 , G01R19/10 , H03K5/24 , H03M1/182 , H03M1/365 , H03M1/66
摘要： A measurement circuit for providing the maximum and/or minimum voltage of a time-variant electrical input signal is presented. The measurement circuit contains a voltage reference unit to provide voltage reference signals and a comparator unit comprising multiple comparators. Each comparator receiving the electrical input signal at a first comparator input and a different voltage reference signal from the voltage reference unit at its second comparator input. The comparator unit provides comparator output signals based on said electrical input signal and said voltage reference signals. A logic unit receives the comparator output signals and provides a voltage output signal indicative of the maximum and/or minimum voltage of the electrical input signal based on the comparator output signals.The logic unit provides adaptation information to the voltage reference entity. The is adaptation information is dependent on the comparator output signals. The voltage reference unit adapts the voltage reference signals based on the adaption information.
摘要翻译：提供了用于提供时变电输入信号的最大和/或最小电压的测量电路。测量电路包含提供电压参考信号的电压参考单元和包括多个比较器的比较器单元。每个比较器在第一比较器输入处接收电输入信号，并在其第二比较器输入处接收来自电压参考单元的不同参考电压信号。比较器单元基于所述电输入信号和所述电压参考信号提供比较器输出信号。逻辑单元接收比较器输出信号，并且基于比较器输出信号提供表示电输入信号的最大和/或最小电压的电压输出信号。逻辑单元向电压参考实体提供自适应信息。自适应信息取决于比较器的输出信号。电压基准单元根据适应信息适应电压参考信号。

10. 发明授权

US09344106B2 ADC calibration 有权
标题翻译： ADC校准
公开(公告)号：US09344106B2
公开(公告)日：2016-05-17
申请号：US14570725
申请日：2014-12-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
IPC分类号： H03M1/10 , H03M1/36
CPC分类号： H03M1/1009 , H03M1/1004 , H03M1/365
摘要： An analog-to-digital converter (ADC) includes a plurality of comparators connected to the ADC. The ADC further includes a plurality of switches, wherein switches connected to a corresponding comparator of the plurality of comparators are configured to alternate the corresponding comparator between normal operation and a calibration configuration. The ADC further includes at least one comparator of the plurality of comparators other than the corresponding comparator is configured for normal operation if the corresponding comparator is configured for calibration.
摘要翻译：模数转换器（ADC）包括连接到ADC的多个比较器。 ADC还包括多个开关，其中连接到多个比较器的相应比较器的开关被配置为在正常操作和校准配置之间交替对应的比较器。如果对应的比较器被配置为用于校准，则ADC还包括多个比较器中的除了对应的比较器之外的至少一个比较器用于正常操作。

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