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1. 发明授权

US09633158B1 Selectable reconfiguration for dynamically reconfigurable IP cores 有权
公开(公告)号：US09633158B1
公开(公告)日：2017-04-25
申请号：US14538784
申请日：2014-11-11
申请人： ALTERA CORPORATION
发明人： Jakob Raymond Jones , Prasanna Padmanabhan
IPC分类号： H01L27/118 , G06F17/50 , H01L27/02 , G06F15/80 , H01L27/115 , H01L23/528
CPC分类号： G06F17/5068 , G06F15/8015 , G06F17/50 , G06F17/5054 , G06F2217/66 , H01L23/528 , H01L27/115 , H01L27/118 , H01L27/11807 , H03K19/17728
摘要： Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.

2. 发明申请

US20160006780A1 METHOD FOR PROCESSING DATA STREAMS INCLUDING TIME-CRITICAL MESSAGES OF A POWER NETWORK 审中-公开
标题翻译：用于处理包括电力网络的时间关键信息的数据流的方法
公开(公告)号：US20160006780A1
公开(公告)日：2016-01-07
申请号：US14789110
申请日：2015-07-01
申请人： ABB TECHNOLOGY AG
发明人： Thomas LOCHER , Alexandru MOGA
IPC分类号： H04L29/06 , H04L12/855 , H04L29/08
CPC分类号： G06F15/8015 , H04L49/00
摘要： A method is disclosed for processing data stream within a time constraint by a stream processing network having a plurality of processing elements. The method includes determining a processing unit, by selecting at least one of the plurality of processing elements, for transmitting next data items of the data stream; collecting system information of the processing unit, wherein the system information includes load information of the selected processing element; adapting, based on the system information, a sending rate of the data stream; discarding, by the processing unit, data items of the data stream that would not be processed within the time constraint; and sending, by the processing unit, data items of the data stream that would be processed within the time constraint.
摘要翻译：公开了一种用于在具有多个处理元件的流处理网络的时间约束内处理数据流的方法。该方法包括：通过选择多个处理元件中的至少一个来确定处理单元，以发送数据流的下一个数据项; 收集所述处理单元的系统信息，其中所述系统信息包括所选择的处理单元的负载信息; 根据系统信息调整数据流的发送速率; 由处理单元丢弃在时间限制内将不被处理的数据流的数据项; 并且由处理单元发送将在时间约束内处理的数据流的数据项。

3. 发明申请

US20150363357A1 MEMORY CONTROLLER AND SIMD PROCESSOR 审中-公开
标题翻译：内存控制器和SIMD处理器
公开(公告)号：US20150363357A1
公开(公告)日：2015-12-17
申请号：US14834282
申请日：2015-08-24
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Shorin KYO
IPC分类号： G06F15/80
CPC分类号： G06F15/8007 , G06F15/8015
摘要： Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit.
摘要翻译：用于抑制在SIMD处理器中的外部部分和多个处理器元件之间的多个矩形区域中交换二维数据时发生的SIMD处理器效率的下降的技术，使得一个矩形区域对应于一个处理器元件。在SIMD处理器中，存储器控制器中的地址存储单元能够通过利用控制处理器在外部存储器中设定N个地址Ai（i = 1〜N）。参数存储单元能够利用控制处理器来设定第一参数OSV，第二参数W和第三参数L. 数据传送单元基于地址存储单元和参数存储单元的内容，在外部存储器和包含在可应用的SIMD处理器中的N个处理器元件中的缓冲器之间执行数据传送。

4. 发明授权

US09053225B2 Data processing apparatus, data processing method, and storage medium 有权
标题翻译：数据处理装置，数据处理方法和存储介质
公开(公告)号：US09053225B2
公开(公告)日：2015-06-09
申请号：US13114155
申请日：2011-05-24
申请人： Isao Sakamoto , Hisashi Ishikawa
发明人： Isao Sakamoto , Hisashi Ishikawa
IPC分类号： H04L12/26 , G06F13/36 , G06F15/173
CPC分类号： G06F13/36 , G06F13/37 , G06F15/173 , G06F15/8015
摘要： A data processing apparatus comprising: a determination unit to determine whether data input from input/output module is data to be processed by a plurality of processing modules in a setting order; and a switching unit to switch a first data and second data processing path, so that when the determination unit determines that the data input from the input/output module is not data to be processed by the processing modules in the setting order, the communication modules circulate data via the first data processing path used to transfer the data in an order in which the communication modules are connected, and otherwise, the communication modules circulate data via the second data processing path used to control the communication modules to transfer the data in the setting order.
摘要翻译：一种数据处理装置，包括：确定单元，确定从输入/输出模块输入的数据是否是由多个处理模块以设定顺序处理的数据; 以及切换单元，用于切换第一数据和第二数据处理路径，使得当确定单元确定从输入/输出模块输入的数据不是处理模块按照设置顺序处理的数据时，通信模块通过用于以通信模块连接的顺序传送数据的第一数据处理路径循环数据，否则，通信模块经由用于控制通信模块的第二数据处理路径循环数据，以将数据传送到设置顺序。

5. 发明申请

US20150143081A1 PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF 审中-公开
标题翻译：支持多模和多模支持方法的处理器
公开(公告)号：US20150143081A1
公开(公告)日：2015-05-21
申请号：US14606240
申请日：2015-01-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU
IPC分类号： G06F15/80 , G06F9/30
CPC分类号： G06F15/8015 , G06F9/30058 , G06F9/3804 , G06F9/3851 , G06F9/3887 , G06F9/3889
摘要： Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
摘要翻译：实施例包括能够支持多模式和相应方法的处理器。处理器包括前端单元，多个前端单元的多个处理元件; 以及控制器，被配置为确定是否由于条件分支而发生线程发散。如果存在线程发散，则处理器可以设置控制信息以使用当前激活的前端单元来控制处理元件。如果没有，则处理器可以使用当前激活的前端单元来设置控制信息以控制处理元件。

6. 发明授权

US08656143B2 Variable clocked heterogeneous serial array processor 有权
标题翻译：可变时钟异构串行数组处理器
公开(公告)号：US08656143B2
公开(公告)日：2014-02-18
申请号：US12699548
申请日：2010-02-03
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F9/22
CPC分类号： G06F1/12 , G06F1/06 , G06F9/30014 , G06F9/30032 , G06F15/7867 , G06F15/8015 , G11C11/405
摘要： A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.
摘要翻译：串行阵列处理器可以具有执行单元，其由多个单位算术逻辑单元（ALU）组成，并且可以通过串行访问和处理存储器中的所有字的子集来执行并行操作，一位同时处理器的指令单元以与执行单元正交的方式一次预取下一个指令，一个字。

7. 发明授权

US08169440B2 Parallel data processing apparatus 有权
标题翻译：并行数据处理装置
公开(公告)号：US08169440B2
公开(公告)日：2012-05-01
申请号：US11754901
申请日：2007-05-29
申请人： Dave Stuttard , Dave Williams , Eamon O'Dea , Gordon Faulds , John Rhoades , Ken Cameron , Phil Atkin , Paul Winser , Russell David , Ray McConnell , Tim Day , Trey Greer
发明人： Dave Stuttard , Dave Williams , Eamon O'Dea , Gordon Faulds , John Rhoades , Ken Cameron , Phil Atkin , Paul Winser , Russell David , Ray McConnell , Tim Day , Trey Greer
IPC分类号： G06F15/80 , G06F15/00 , G06T1/20 , G09G5/00
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/3004 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F15/80 , G06F15/8007 , G06F15/8015 , G06T1/20
摘要： A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.
摘要翻译：公开了一种处理与几何图元有关的数据的方法。每个基元具有多个顶点。该方法使用彼此并行的多个处理元件，并且包括将各个顶点数据分配给每个处理元件上的处理元件，并且彼此并行地，对顶点数据执行至少一个处理步骤以产生经处理的顶点数据和处理元素之间传送处理的顶点数据，以便组合原始数据。

8. 发明申请

US20120030448A1 SINGLE INSTRUCTION MULTIPLE DATE (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS 审中-公开
标题翻译：具有多个处理元件的单个指令多个日期（SIMD）处理器由环形总线互连
公开(公告)号：US20120030448A1
公开(公告)日：2012-02-02
申请号：US13203809
申请日：2009-09-25
申请人： Hanno Lieske
发明人： Hanno Lieske
IPC分类号： G06F9/30 , G06F9/315 , G06F9/305
CPC分类号： G06F15/8015 , G06F15/163 , G06F15/17337 , H04N5/44 , H04N19/107 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/86
摘要： A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data.
摘要翻译：一种具有多个处理元件的单指令多数据（SIMD）处理器，包括：分割单元，用于将数据存储器中的只读参数数据的地址分割成与第一部分和第二部分相对应的比特位置处理器元件的数量; 以及比较单元，用于比较在环形总线上从根据第一部分的地址处的内部存储器获取的只读参数数据与自身处理器单元位置之间的差异以及要访问的只读参数数据的全局地址的一部分，指定处理器元件的环中的位置的部分，其中存储要访问的只读参数数据并对应于第二部分，以使其他处理器元件采用只读参数数据。

9. 发明授权

US08078834B2 Processor architectures for enhanced computational capability 有权
标题翻译：用于增强计算能力的处理器架构
公开(公告)号：US08078834B2
公开(公告)日：2011-12-13
申请号：US12008220
申请日：2008-01-09
申请人： Douglas Garde
发明人： Douglas Garde
IPC分类号： G06F15/173
CPC分类号： G06F15/8015
摘要： A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.
摘要翻译：数字信号处理器包括被配置为基于存储的程序发布指令的控制块，以及包括两个或更多个计算引擎的计算阵列，所述计算引擎被配置为使得每个发出的指令在计算引擎的至少一个子集的连续计算引擎中执行在连续的时候。数字信号处理器可以与控制处理器或独立处理器一起使用。计算阵列可以被配置成使得每个发出的指令在连续的时间内流过计算引擎的至少一个子集的连续的计算引擎。

10. 发明申请

US20110156875A1 Apparatus for and Method of Processing Data 有权
标题翻译：数据处理装置及方法
公开(公告)号：US20110156875A1
公开(公告)日：2011-06-30
申请号：US12978321
申请日：2010-12-23
申请人： Naozumi Sugimura
发明人： Naozumi Sugimura
IPC分类号： H04Q5/22
CPC分类号： G06F15/8015
摘要： An apparatus for processing data includes a plurality of signal processing units, each signal processing unit including a register that stores identification (ID) information to store a parameter, the signal processing units operative to sequentially perform an operation of storing the parameter or an operation of processing a signal in response to a mode control signal; a storage unit; a data reading unit that selectively reads parameter information or processing data from the storage unit; a data writing unit that selectively writes data corresponding to a data signal output by each of the signal processing units in the storage unit; and a control unit that outputs the mode control signal to each of the signal processing units. During the operation of storing the parameter, when the data signal corresponds to the ID information, each of the signal processing units writes a parameter included in the data signal in the register.
摘要翻译：一种用于处理数据的装置包括多个信号处理单元，每个信号处理单元包括存储用于存储参数的标识（ID）信息的寄存器，所述信号处理单元可操作以顺序执行存储该参数的操作或操作响应于模式控制信号处理信号; 存储单元; 数据读取单元，其从所述存储单元选择性地读取参数信息或处理数据; 数据写入单元，其选择性地将对应于由每个信号处理单元输出的数据信号的数据写入存储单元; 以及控制单元，其将模式控制信号输出到每个信号处理单元。在存储参数的操作期间，当数据信号对应于ID信息时，每个信号处理单元将包括在数据信号中的参数写入寄存器。

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