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1. 发明授权

US11144480B2 Atomic instruction having a local scope limited to an intermediate cache level 有权
公开(公告)号：US11144480B2
公开(公告)日：2021-10-12
申请号：US15452073
申请日：2017-03-07
申请人： KALRAY
发明人： Benoit Dupont De Dinechin , Marta Rybczynska , Vincent Ray
IPC分类号： G06F12/14 , G06F9/52 , G06F9/30 , G06F12/0804 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

2. 发明申请

US20160134725A1 METHOD FOR DISPATCHING NETWORK FRAMES AMONG PROCESSING RESOURCES 审中-公开
标题翻译：在处理资源中分配网络框架的方法
公开(公告)号：US20160134725A1
公开(公告)日：2016-05-12
申请号：US14932679
申请日：2015-11-04
申请人： KALRAY
发明人： Patrice COUVERT , Marta RYBCZYNSKA , Siméon MARIJON , Yann KALEMKARIAN , Benoît GANNE , Alexandre BLAMPEY
IPC分类号： H04L29/06
CPC分类号： H04L69/22 , H04L49/3009 , H04L49/351 , H04L67/42 , H04L69/12 , H04L69/161
摘要： The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.
摘要翻译：本发明涉及一种处理到达网络接口的数据帧的方法，包括在网络接口中实现的以下步骤：存储一组目标位置（tgtPOS），在期望的至少一个参数的帧中的位置子网（ETH_TYPE）和表征客户端 - 服务器会话的参数（SRC_IP，DST_IP）; 存储子帧参数的期望值（xpVAL）; 接收当前帧并将在子帧参数的位置处接收的值（xtVAL）与期望值进行比较; 如果相等，则从在会话参数的位置接收的值计算索引（IDX）; 并将当前帧路由到与索引相关联的处理资源。

3. 发明申请

US20140301207A1 SYSTEM FOR TRANSMITTING CONCURRENT DATA FLOWS ON A NETWORK 有权
标题翻译：在网络上发送并发数据流的系统
公开(公告)号：US20140301207A1
公开(公告)日：2014-10-09
申请号：US14367050
申请日：2012-12-19
申请人： KALRAY
发明人： Yves Durand , Alexandre Blampey
IPC分类号： H04L12/835
CPC分类号： H04L47/30 , H04L12/5601 , H04L47/6255 , H04L47/628 , H04L49/9036 , H04L2012/5679
摘要： A system for transmitting concurrent data flows on a network, includes a memory containing data of data flows; a plurality of queues assigned respectively to the data flows, organized to receive the data as atomic transmission units; a flow regulator to poll the queues in sequence and, if the polled queue contains a full transmission unit, transmitting the unit on the network at a nominal flow-rate of the network; a sequencer to poll the queues in a round-robin manner and enable a data request signal when the filling level of the polled queue is below a threshold common to all queues, which threshold is greater than the size of the largest transmission unit; and a direct memory access configured to receive the data request signal and respond thereto by transferring data from the memory to the corresponding queue at a nominal speed of the system, up to the common threshold.
摘要翻译：一种用于在网络上发送并发数据流的系统，包括：包含数据流数据的存储器; 分配给数据流的多个队列，被组织以接收作为原子传输单元的数据; 流量调节器按顺序轮询队列，如果轮询队列包含完整传输单元，则以网络的标称流量在网络上传输单元; 定序器，以循环方式轮询队列，并且当轮询队列的填充级别低于所有队列共有的阈值时，启用数据请求信号，该阈值大于最大传输单元的大小; 以及直接存储器访问，被配置为接收数据请求信号并且通过以系统的标称速度将数据从存储器传送到对应的队列来响应，直到公共阈值。

4. 发明授权

US11489544B2 Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial 有权
公开(公告)号：US11489544B2
公开(公告)日：2022-11-01
申请号：US17217640
申请日：2021-03-30
申请人： Kalray
发明人： Nicolas Brunie
IPC分类号： H03M13/09
摘要： A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.

5. 发明授权

US11294627B2 Floating point dot-product operator with correct rounding 有权
公开(公告)号：US11294627B2
公开(公告)日：2022-04-05
申请号：US16946526
申请日：2020-06-25
申请人： Kalray
发明人： Nicolas Brunie
IPC分类号： G06F7/487 , G06F7/499 , H03M7/24
摘要： The disclosure relates to a hardware operator for dot-product computation, comprising a plurality of multipliers each receiving two multiplicands in the form of floating-point numbers encoded in a first precision format; an alignment circuit associated with each multiplier, configured to, based on the exponents of the corresponding multiplicands, convert the result of the multiplication into a respective fixed-point number having a sufficient number of bits to cover the full dynamic range of the multiplication; and a multi-adder configured to add without loss the fixed-point numbers provided by the multipliers, providing a sum in the form of a fixed-point number.

6. 发明授权

US10175989B2 VLIW type instruction packet structure and processor suitable for processing such an instruction packet 有权
公开(公告)号：US10175989B2
公开(公告)日：2019-01-08
申请号：US15312961
申请日：2015-04-27
申请人： KALRAY
发明人： Renaud Ayrignac , Vincent Ray , Benoît Dupont De Dinechin
IPC分类号： G06F8/41 , G06F9/30 , G06F9/38
摘要： A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

7. 发明申请

US20170149908A1 TOKEN BUCKET FLOW-RATE LIMITER 审中-公开
公开(公告)号：US20170149908A1
公开(公告)日：2017-05-25
申请号：US15356151
申请日：2016-11-18
申请人： KALRAY
发明人： Duco VAN AMSTEL , Alexandre BLAMPEY , Benoit DUPONT DE DINECHIN
IPC分类号： H04L29/08 , H04L12/24 , H04L12/26
CPC分类号： H04L67/146 , H04L41/0896 , H04L43/0894 , H04L47/215
摘要： A token bucket flow rate limiter is provided for a data transmission, comprising a token counter configured to be incremented at a rate determining the average flow rate of the transmission; a frequency divider connected to control incrementing of the token counter from a clock, the divider having an integer division factor; and a modulator configured to alternate the division factor between two different integers so as to make the resulting average flow rate tend to a programmed flow rate comprised between two boundary flow rates respectively corresponding to the two integers.

8. 发明申请

US20140301206A1 SYSTEM FOR TRANSMITTING CONCURRENT DATA FLOWS ON A NETWORK 审中-公开
标题翻译：在网络上发送并发数据流的系统
公开(公告)号：US20140301206A1
公开(公告)日：2014-10-09
申请号：US14366886
申请日：2012-12-19
申请人： KALRAY
发明人： Yves Durand , Alexandre Blampey
IPC分类号： H04L12/801
CPC分类号： H04L47/29 , H04L12/5601 , H04L47/6255 , H04L47/628 , H04L49/9036 , H04L2012/5679
摘要： A system for transmitting concurrent data flows on a network includes a memory containing the data of the data flows; a plurality of queues assigned respectively to the data flows, organized to receive the data as atomic transmission units; a flow regulator configured to poll the queues in sequence and, if the polled queue contains a full transmission unit, transmitting the unit on the network at a nominal flow-rate of the network; a queue management circuit configured to individually fill each queue from the data contained in the memory, at a nominal speed of the system, up to a threshold common to all queues; a configuration circuit configurable to provide the common threshold of the queues; and a processor programmed to produce the data flows and manage their assignment to the queues, and connected to the configuration circuit to dynamically adjust the threshold according to the largest transmission unit used in the flows being transmitted.
摘要翻译：用于在网络上发送并发数据流的系统包括：包含数据流的数据的存储器; 分配给数据流的多个队列，被组织以接收作为原子传输单元的数据; 流量调节器被配置为依次轮询队列，并且如果被轮询的队列包含完整的传输单元，则以网络的标称流量在网络上传送该单元; 队列管理电路被配置为以系统的标称速度从包含在存储器中的数据分别填充每个队列直到所有队列共同的阈值; 配置电路，可配置为提供队列的公共阈值; 以及处理器，其被编程为产生数据流并管理其对队列的分配，并且连接到配置电路以根据在所发送的流中使用的最大传输单元来动态地调整阈值。

9. 发明申请

US20210200904A1 PROCESSOR WITH A CONFIGURABLE DISTRIBUTION OF PRIVILEGED RESOURCES AND EXCEPTIONS BETWEEN PROTECTION RINGS 有权
公开(公告)号：US20210200904A1
公开(公告)日：2021-07-01
申请号：US17139662
申请日：2020-12-31
申请人： Kalray
发明人： Pierre GUIRONNET DE MASSAS , Vincent RAY , Benoit DUPONT DE DINECHIN
IPC分类号： G06F21/71
摘要： A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

10. 发明申请

US20200210248A1 CONFIGURABLE INTER-PROCESSOR SYNCHRONIZATION SYSTEM 审中-公开
公开(公告)号：US20200210248A1
公开(公告)日：2020-07-02
申请号：US16729118
申请日：2019-12-27
申请人： Kalray
发明人： Benoit Dupont de Dinechin , Arnaud Odinot , Vincent Ray
IPC分类号： G06F9/52 , G06F9/30 , G06F9/54
摘要： The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.

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