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2. 发明申请

US20150339173A1 HARDWARE SYNCHRONIZATION BARRIER BETWEEN PROCESSING UNITS 有权
标题翻译：加工单位之间的硬件同步障碍
公开(公告)号：US20150339173A1
公开(公告)日：2015-11-26
申请号：US14721695
申请日：2015-05-26
申请人： KALRAY
发明人： Thomas CHAMPSEIX , Benoît DUPONT DE DINECHIN , Pierre GUIRONNET DE MASSAS
IPC分类号： G06F9/52
CPC分类号： G06F9/522 , G06F9/52 , G06F9/54
摘要： A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
摘要翻译：一种用于同步多个处理单元的方法，包括以下步骤：在目标处理单元中配置同步寄存器，使得其内容仅被写入同步寄存器中的字设置的位重写; 将所述同步寄存器的不同位位置分配给每个处理单元; 并在每个处理单元中执行程序线程。当当前处理单元的程序线程到达同步点时，该方法包括在目标处理单元的同步寄存器中写入分配给当前处理单元的位位置并暂停程序线程的单词。当分配给处理单元的所有位都被设置在同步寄存器中时，恢复暂停的程序线程。

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