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1. 发明申请

US20170192792A1 VLIW TYPE INSTRUCTION PACKET STRUCTURE AND PROCESSOR SUITABLE FOR PROCESSING SUCH AN INSTRUCTION PACKET 审中-公开
公开(公告)号：US20170192792A1
公开(公告)日：2017-07-06
申请号：US15312961
申请日：2015-04-27
申请人： KALRAY
发明人： Renaud AYRIGNAC , Vincent RAY , Benoît DUPONT DE DINECHIN
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F8/445 , G06F9/30149 , G06F9/3855 , G06F9/3885
摘要： A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

2. 发明申请

US20150339256A1 INTER-PROCESSOR SYNCHRONIZATION SYSTEM 审中-公开
标题翻译：交互处理器同步系统
公开(公告)号：US20150339256A1
公开(公告)日：2015-11-26
申请号：US14716298
申请日：2015-05-19
申请人： KALRAY
发明人： Benoît DUPONT DE DINECHIN , Vincent RAY
IPC分类号： G06F13/42 , G06F15/82
摘要： An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor.
摘要翻译：使用点对点链路的处理器间同步方法包括以下步骤：定义源处理器和目标处理器之间的点对点同步信道; 在所述源处理器中执行期望与所述同步信道相关联的通知的等待命令，其中所述等待命令被设计为停止所述源处理器直到接收到所述通知; 在所述目标处理器中执行通知命令，所述通知命令被设计为通过所述点对点链路传送由所述源处理器预期的通知; 在所述目标处理器中执行期望与所述同步信道相关联的通知的等待命令，其中所述等待命令被设计为停止所述目标处理器直到接收到所述通知; 以及在所述源处理器中执行通知命令，所述通知命令被设计成通过所述点对点链路传送由所述目标处理器预期的通知。

3. 发明申请

US20210200904A1 PROCESSOR WITH A CONFIGURABLE DISTRIBUTION OF PRIVILEGED RESOURCES AND EXCEPTIONS BETWEEN PROTECTION RINGS 有权
公开(公告)号：US20210200904A1
公开(公告)日：2021-07-01
申请号：US17139662
申请日：2020-12-31
申请人： Kalray
发明人： Pierre GUIRONNET DE MASSAS , Vincent RAY , Benoit DUPONT DE DINECHIN
IPC分类号： G06F21/71
摘要： A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

4. 发明申请

US20170255571A1 ATOMIC INSTRUCTION HAVING A LOCAL SCOPE LIMITED TO AN INTERMEDIATE CACHE LEVEL 审中-公开
公开(公告)号：US20170255571A1
公开(公告)日：2017-09-07
申请号：US15452073
申请日：2017-03-07
申请人： KALRAY
发明人： Benoit DUPONT DE DINECHIN , Marta RYBCZYNSKA , Vincent RAY
IPC分类号： G06F12/14 , G06F12/0862 , G06F12/0811 , G06F12/0815
CPC分类号： G06F12/1475 , G06F9/3004 , G06F9/52 , G06F12/0804 , G06F12/0811 , G06F12/0815 , G06F12/0862 , G06F2212/1052 , G06F2212/283 , G06F2212/602 , G06F2212/621
摘要： The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

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