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1. 发明授权

US08488623B2 Scalable interconnect modules with flexible channel bonding 有权
公开(公告)号：US08488623B2
公开(公告)日：2013-07-16
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16 , H04J3/22 , H04J3/06
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

2. 发明申请

US20090161738A1 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US20090161738A1
公开(公告)日：2009-06-25
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

3. 发明申请

US20120027026A1 SCALABLE INTERCONNECT MODULES WITH FLEXIBLE CHANNEL BONDING 有权
标题翻译：具有灵活通道连接的可扩展互连模块
公开(公告)号：US20120027026A1
公开(公告)日：2012-02-02
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
摘要翻译：本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。这有利地允许优化用于两种类型的通道结合的配置。在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。这种去耦有利地消除了先前架构的刚性约束。

4. 发明授权

US09559881B2 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38 , H04L25/14
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

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