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1. 发明申请

US20120027026A1 SCALABLE INTERCONNECT MODULES WITH FLEXIBLE CHANNEL BONDING 有权
标题翻译：具有灵活通道连接的可扩展互连模块
公开(公告)号：US20120027026A1
公开(公告)日：2012-02-02
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
摘要翻译：本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。这有利地允许优化用于两种类型的通道结合的配置。在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。这种去耦有利地消除了先前架构的刚性约束。

2. 发明授权

US08488623B2 Scalable interconnect modules with flexible channel bonding 有权
公开(公告)号：US08488623B2
公开(公告)日：2013-07-16
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16 , H04J3/22 , H04J3/06
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

3. 发明授权

US08059677B1 Scalable channel bundling with adaptable channel synchronization 有权
标题翻译：可扩展的频道绑定，具有适应性的频道同步
公开(公告)号：US08059677B1
公开(公告)日：2011-11-15
申请号：US12427960
申请日：2009-04-22
申请人： Keith Duwel , Michael Menghui Zheng , Lana May Chan , Showi-Min Shen
发明人： Keith Duwel , Michael Menghui Zheng , Lana May Chan , Showi-Min Shen
IPC分类号： H04J3/16 , H04J3/22 , G06F17/50 , G06F7/38
CPC分类号： G06F17/505
摘要： Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits (“FIFOs”) located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.
摘要翻译：公开了促进通道捆绑的结构和方法。在一个实施例中，信号分配电路包括数据路径，其中至少两个寄存器耦合到一组数据信道集合中的相邻数据信道集合。在另一个实施例中，自交换电路允许信道集合中的信道在束宽信号已经被同步分布到分组中的所有信道集之后从束范围信号切换到本地产生的信号。在特定实施例中，信号分配电路用于分配分频时钟信号。在另一特定实施例中，信号分配电路用于分配位于通道组束中的每个数据通道的通道中的先进先出电路（“FIFO”）的使能信号。在一个实施例的一个特定方面，跨越信道集束的FIFO读和写操作被启动，使得每个信道集合中读指针信号和写指针信号之间的差异是相同的。

4. 发明授权

US09436250B1 Apparatus for improving power consumption of communication circuitry and associated methods 有权
标题翻译：用于改善通信电路和相关方法的功耗的装置
公开(公告)号：US09436250B1
公开(公告)日：2016-09-06
申请号：US13330635
申请日：2011-12-19
申请人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
发明人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： H03L7/0807 , G06F1/32 , G06F1/3278 , G06F1/3296 , G06F11/0736 , G06F11/076 , G06F11/079 , H03K19/0008 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H04B17/309 , Y02D10/157
摘要： An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
摘要翻译：集成电路（IC）包括通信电路，体偏置发生器和控制器。通信电路包括物理介质连接（PMA）和物理编码子层（PCS）。身体偏置发生器向PMA和PCS提供身体偏置信号。控制器控制身体偏置发生器，使得身体偏置信号被控制以提高通信电路的功率消耗。

5. 发明授权

US09736086B1 Multi-function, multi-protocol FIFO for high-speed communication 有权
公开(公告)号：US09736086B1
公开(公告)日：2017-08-15
申请号：US13098361
申请日：2011-04-29
申请人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

6. 发明授权

US09170952B1 Configurable multi-standard device interface 有权
标题翻译：可配置的多标准设备接口
公开(公告)号：US09170952B1
公开(公告)日：2015-10-27
申请号：US13338707
申请日：2011-12-28
申请人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
发明人： Divya Vijayaraghavan , Vinson Chan , Keith Duwel , Chong H. Lee
IPC分类号： G06F13/00 , G06F12/02 , G06F12/08 , G06F13/12 , G06F13/14 , G06F11/00 , H01L25/00 , H04J3/06
CPC分类号： G06F12/0862 , G06F13/00 , H03K19/17744
摘要： A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.
摘要翻译：可配置接口包括发射器模块和接收器模块，每个发送器模块和接收器模块被配置为根据至少三个不同的接口标准进行操作。所述可配置接口还包括接口模块，所述接口模块被配置为确定耦合到所述可配置接口的PMA的物理介质连接（PMA）标准，并基于所述PMA标准激活所述可配置接口的至少一个组件。在这种安排中，设备接口支持CAUI-4标准。

7. 发明授权

US08554959B2 Apparatus and methods for communicating with programmable devices 有权
标题翻译：用于与可编程器件通信的装置和方法
公开(公告)号：US08554959B2
公开(公告)日：2013-10-08
申请号：US13461592
申请日：2012-05-01
申请人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
发明人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/10 , G06F17/5054 , H03K19/1776
摘要： A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
摘要翻译：电路装置包括可编程逻辑器件。可编程逻辑器件包括配置逻辑电路。可编程逻辑器件还包括可配置互连。电路装置还包括被配置为向可编程逻辑器件提供数据的存储装置。存储装置经由双向接口与可编程逻辑装置进行通信。

8. 发明授权

US07705628B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
标题翻译：可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器
公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
申请人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
发明人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译：具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。多个逻辑块中的每一个还包括一个或多个逻辑元件。逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

9. 发明授权

US07702893B1 Integrated circuits with configurable initialization data memory addresses 失效
标题翻译：具有可配置初始化数据存储器地址的集成电路
公开(公告)号：US07702893B1
公开(公告)日：2010-04-20
申请号：US11525657
申请日：2006-09-22
申请人： Nicholas J. Rally , Dirk A. Reese , Keith Duwel
发明人： Nicholas J. Rally , Dirk A. Reese , Keith Duwel
IPC分类号： G06F15/177
CPC分类号： G06F9/4401
摘要： Systems and methods are provided for avoiding memory address conflicts in systems containing shared memory. Upon system power up, programmable logic device integrated circuits, microprocessors, and other integrated circuits with processing capabilities are provided with unique initialization data memory addresses. Each unique initialization data memory address corresponds to a respective non-overlapping block of memory in the shared memory. During initialization operations, the integrated circuits retrieve initialization data from the shared memory using the unique initialization data memory addresses. The integrated circuits can be organized using a master-slave architecture. The master can load the initialization data memory addresses into the slave integrated circuits using communications circuitry that is active after the slaves have powered up but before the slaves have been initialized.
摘要翻译：提供了系统和方法，用于避免包含共享内存的系统中的内存地址冲突。在系统上电时，可编程逻辑器件集成电路，微处理器和具有处理能力的其他集成电路提供唯一的初始化数据存储器地址。每个唯一的初始化数据存储器地址对应于共享存储器中相应的不重叠的存储器块。在初始化操作期间，集成电路使用唯一的初始化数据存储器地址从共享存储器检索初始化数据。可以使用主从架构来组织集成电路。主机可以使用通信电路将初始化数据存储器地址加载到从属集成电路中，这些通信电路在从机通电之后，但在从站已初始化之前处于活动状态。

10. 发明授权

US07287189B1 I/O configuration and reconfiguration trigger through testing interface 有权
标题翻译：通过测试界面进行I / O配置和重新配置触发
公开(公告)号：US07287189B1
公开(公告)日：2007-10-23
申请号：US10603888
申请日：2003-06-25
申请人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
发明人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
IPC分类号： G06F11/00
CPC分类号： G01R31/318572
摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.
摘要翻译：可重构设备在测试期间从诊断接口加载I / O配置信息。该设备包括用于与其他设备通信值的可配置I / O连接。诊断接口将I / O连接的值传送给测试仪。设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式接口，从而修改I / O连接的配置。该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。诊断接口可以是JTAG接口。

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