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    • 1. 发明授权
    • Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof
    • 在对熔丝电路编程之前能够测试故障的半导体存储器及其方法
    • US07688659B2
    • 2010-03-30
    • US12127161
    • 2008-05-27
    • Kaoru MoriJun OhnoHiroyuki Kobayashi
    • Kaoru MoriJun OhnoHiroyuki Kobayashi
    • G11C29/00
    • G11C29/26G11C7/1045G11C11/401G11C29/02G11C29/025G11C2029/5006G11C2029/5602
    • Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.
    • 每个程序电路根据程序状态输出指示第一或第二操作规范的操作规范信号。 每个规格改变电路由相应的块选择信号设置,并输出指示第二操作规范的操作指定信号。 每个定时控制电路根据操作指定信号改变位线的预充电控制信号的输出定时。 通过来自规范改变电路的操作规范信号,在对程序电路进行编程之前可以在每个存储器块中检测到故障。 此后,程序电路可以解除故障。 可以通过块选择信号为每个存储器块设置预充电控制信号的输出定时,而不布线用于设置每个规格改变电路的专用信号线。 因此,可以使芯片尺寸的增加最小化。
    • 2. 发明申请
    • Semiconductor memory and refresh cycle control method
    • 半导体存储器和刷新周期控制方法
    • US20070268766A1
    • 2007-11-22
    • US11797817
    • 2007-05-08
    • Kaoru Mori
    • Kaoru Mori
    • G11C11/34G11C7/04G11C7/00
    • G11C11/406G11C7/04G11C11/401G11C11/40626G11C29/02G11C29/028G11C2029/0409G11C2029/5002G11C2211/4061G11C2211/4067
    • A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
    • 一种半导体存储器和刷新周期控制方法,通过根据半导体存储器的温度适当地改变刷新周期来减少待机电流。 温度检测部检测半导体存储器的温度。 当半导体存储器的温度达到预定的周期变化温度时,循环变化控制部分发送用于改变刷新周期的循环改变信号。 刷新定时信号生成部生成刷新定时信号,根据周期变更信号改变刷新定时信号的周期。 恒流产生电路产生用于产生刷新定时信号的电流。 低温恒流设定电路表示在半导体存储器的温度低于或等于循环变化温度的情况下产生的电流的电平。 高温恒流设定电路表示在半导体存储器的温度高于循环变化温度的情况下产生的电流的电平。
    • 3. 发明申请
    • Magnetic memory adopting synthetic antiferromagnet as free magnetic layer
    • 磁记忆采用合成反铁磁体作为自由磁性层
    • US20060038213A1
    • 2006-02-23
    • US11208370
    • 2005-08-19
    • Kaoru MoriTetsuhiro SuzukiYoshiyuki FukumotoSadahiko Miura
    • Kaoru MoriTetsuhiro SuzukiYoshiyuki FukumotoSadahiko Miura
    • H01L29/94
    • G11C11/16B82Y25/00H01F10/3254H01F10/3272H01L43/08
    • A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N−1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N−1. The free magnetic layer is designed so that antiferromagnetic coupling(s) between the j-th and (j+1)-th ferromagnetic layers is stronger than that between the first and second ferromagnetic layers, j being any of integers ranging from 2 to N−2.
    • 磁存储器包括:包括自由磁性层的磁阻元件; 第一互连件,其在第一方向上倾斜于所述自由磁性层的容易轴线延伸; 沿与第一方向大致正交的第二方向延伸的第二互连; 以及写入电路,通过在所述第一互连上形成第一写入电流将数据写入所述自由磁性层,然后在所述第二互连上开启第二写入电流,所述第一写入电流导通。 自由磁性层包括:第一至第N铁磁层和N等于或大于4的第一至第(N-1)个非磁性层,第i个非磁性层设置在i 和第(i + 1)个铁磁层,其中i为等于或小于N-1的任意自然数。 自由磁性层被设计成使得第j和第(j + 1)个铁磁层之间的反铁磁耦合比第一和第二铁磁层之间的反铁磁耦合更强,j是从2到N的整数中的任何一个 -2。
    • 4. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US06791354B2
    • 2004-09-14
    • US10032465
    • 2002-01-02
    • Kaoru MoriShinichi YamadaMasato Takita
    • Kaoru MoriShinichi YamadaMasato Takita
    • G06F738
    • G11C11/4076G11C5/143G11C5/147G11C11/4074G11C2207/002G11C2207/2227
    • A plurality of switching transistors is provided, each connects power supply terminals of a plurality of first circuit blocks to a power supply line, respectively. Among the first circuit blocks, the power supply terminals of the first circuit blocks operating at different timings are connected by an internal power supply line. A power supply control circuit simultaneously turns on the switching transistors connected to the internal power supply line, in response to operation(s) of at least any one of the first circuit blocks connected to the internal power supply line. Since the switching transistors can be shared among the first circuit blocks not operating simultaneously, operation speed of the first circuit blocks can be increased. Since a total size of the switching transistors can be made small, standby current can be decreased. Accordingly, a semiconductor integrated circuit operating at a high speed can be constituted without increasing the standby current.
    • 提供多个开关晶体管,每个将多个第一电路块的电源端分别连接到电源线。 在第一电路块中,在不同定时工作的第一电路的电源端子通过内部电源线连接。 响应于连接到内部电源线的至少任一个第一电路块的操作,电源控制电路同时接通连接到内部电源线的开关晶体管。 由于开关晶体管可以在不同时操作的第一电路块之间共享,所以可以增加第一电路块的操作速度。 由于可以使开关晶体管的总体尺寸小,所以可以降低待机电流。 因此,可以在不增加待机电流的情况下构成高速工作的半导体集成电路。