专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06823352B2 Solving a nonlinear equation through interval arithmetic and term consistency 失效
标题翻译：通过间隔算术和项目一致性求解非线性方程
公开(公告)号：US06823352B2
公开(公告)日：2004-11-23
申请号：US09952759
申请日：2001-09-13
申请人： G. William Walster , Eldon R. Hansen
发明人： G. William Walster , Eldon R. Hansen
IPC分类号： G06F738
CPC分类号： G06F17/12
摘要： One embodiment of the present invention provides a system for solving a nonlinear equation through interval arithmetic. During operation, the system receives a representation of the nonlinear equation ƒ(x)=0, as well as a representation of an initial interval, X, wherein this representation of X includes a first floating-point number, XL, for the left endpoint of X, and a second floating-point number, XU, for the right endpoint of X. Next, the system symbolically manipulates the nonlinear equation ƒ(x)=0 to solve for a first term, g1(x), thereby producing a modified equation g1(x)=h1(x), wherein the first term g1(x) can be analytically inverted to produce an inverse function g1−1(x). The system then plugs the initial interval X into the modified equation to produce the equation g1(X′)=h1(X), and solves for X′=g1−1[h1(X)]. Next, the system intersects X′ with the initial interval X to produce a new interval X+, wherein the new interval X+ contains all solutions of the equation ƒ(x)=0 within the initial interval X, and wherein the size of the new interval X+ is less than or equal to the size of the initial interval X.
摘要翻译：本发明的一个实施例提供一种通过间隔算术求解非线性方程的系统。在操作期间，系统接收非线性方程f（x）= 0的表示，以及初始间隔X的表示，其中X的该表示包括用于左端点的第一浮点数XL X的右端点的第二个浮点数XU。接下来，系统象征性地操纵非线性方程f（x）= 0来求解第一项g1（x），从而产生修正方程g1（x）= h1（x），其中第一项g1（x）可以被分析反转以产生反函数g1 -1（x）。然后，系统将初始间隔X插入到修正方程中以产生方程g1（X'）= h1（X），并求解X'= g1 <-1> [h1（X）]。接下来，系统与X'与初始间隔X相交以产生新的间隔X +，其中新间隔X +在初始间隔X内包含方程f（x）= 0的所有解，其中新间隔X <>的大小小于或等于初始间隔X的大小。

2. 发明授权

US06820106B1 Method and apparatus for improving the performance of a floating point multiplier accumulator 失效
标题翻译：提高浮点乘法器累加器性能的方法和装置
公开(公告)号：US06820106B1
公开(公告)日：2004-11-16
申请号：US09604620
申请日：2000-06-27
申请人： Narsing K. Vijayrao , Chi Keung Lee , Sudarshan Kumar
发明人： Narsing K. Vijayrao , Chi Keung Lee , Sudarshan Kumar
IPC分类号： G06F738
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49957 , G06F7/74
摘要： A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.
摘要翻译：一种提高浮点乘法器累加器（FMAC）性能的方法和装置。该方法包括接收三个浮点数并计算第一个浮点数和第二个浮点数的乘积，并加上第三个浮点数以产生一个和值和一个进位值。然后根据和值和进位值计算传播值，杀死值和生成值。同时将总和值加到进位值以创建第一个结果，将和值添加到进位值并递增1以创建第二个结果，将总和值添加到进位值并递增2以创建确定第三结果和小数点位置。然后根据舍入模式和小数点位置选择第一个结果之一，第二个结果和第三个结果。所选结果根据小数点位置进行归一化。该装置包括具有耦合到其的传播，杀死，生成发生器（PKG发生器）的乘法器。加法器，加法器，加二和前导零预测器（LZA）均并联耦合到PKG发生器。四舍五入控制单元耦合到LZA，并且耦合到多路复用器，该多路复用器响应于舍入控制单元输出加法器，加上器和加二乘法器中的一个的结果。归一化移位器耦合到多路复用器和LZA。

3. 发明授权

US06789098B1 Method, data processing system and computer program for comparing floating point numbers 有权
标题翻译：比较浮点数的方法，数据处理系统和计算机程序
公开(公告)号：US06789098B1
公开(公告)日：2004-09-07
申请号：US09693974
申请日：2000-10-23
申请人： Wilco Dijkstra
发明人： Wilco Dijkstra
IPC分类号： G06F738
CPC分类号： G06F7/026 , G06F7/483 , G06F7/49905
摘要： The present invention provides a method, data processing system and computer program for comparing first and second floating point numbers involving providing a hierarchy of tests arranged to identify from said first and second floating point numbers whether said one or more exception conditions exist. Each test is arranged to generate a hit signal if that test predicts that one or more exception conditions exist. If the executed test generates a hit signal and is not the final test in the hierarchy, the method branches to the next test in the hierarchy, executes that test and returns to the step of determining whether the executed test has generated a hit signal. If the executed test generates a hit signal and is the final test in the hierarchy, an exception signal is generated indicating the presence of one or more exception conditions.
摘要翻译：本发明提供了一种用于比较第一和第二浮点数的方法，数据处理系统和计算机程序，所述第一和第二浮点数提供测试层级，其布置成从所述第一和第二浮点数识别是否存在所述一个或多个异常条件。如果该测试预测存在一个或多个异常条件，则每个测试被安排成产生命中信号。如果执行的测试生成命中信号，并且不是层次结构中的最终测试，则该方法分支到层次结构中的下一个测试，执行该测试并返回到确定被执行的测试是否已经产生命中信号的步骤。如果执行的测试生成命中信号并且是层次结构中的最终测试，则产生指示存在一个或多个异常条件的异常信号。

4. 发明授权

US06781407B2 FPGA and embedded circuitry initialization and processing 有权
标题翻译： FPGA和嵌入式电路的初始化和处理
公开(公告)号：US06781407B2
公开(公告)日：2004-08-24
申请号：US10043769
申请日：2002-01-09
申请人： David P. Schultz
发明人： David P. Schultz
IPC分类号： G06F738
CPC分类号： H03K19/17772 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.
摘要翻译：互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。互连逻辑包括互连瓦片，并且还可以包括接口逻辑。互连瓦片提供了固定逻辑电路的输入和/或输出之间的选择性连接以及可编程逻辑结构的互连。接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。在一个操作中，可编程逻辑结构在固定逻辑电路的启动/引导顺序之前被配置。在另一个操作中，固定逻辑电路被启动并用于配置可编程逻辑结构。

5. 发明授权

US06766343B1 Method and apparatus for coordinate system conversions 有权
标题翻译：用于坐标系转换的方法和装置
公开(公告)号：US06766343B1
公开(公告)日：2004-07-20
申请号：US09499061
申请日：2000-02-04
申请人： David M. Bell , Dennis L. Maly , Timothy R. Culp
发明人： David M. Bell , Dennis L. Maly , Timothy R. Culp
IPC分类号： G06F738
CPC分类号： G06T3/00
摘要： A method for converting between source coordinates in a source coordinate system and target coordinates in a target coordinate system includes the step of defining a coordinate system conversion tree extending from a root coordinate system and branching to a plurality of other coordinate-systems including the source and target coordinate systems so that the source and target coordinate systems are connected to a common coordinate system other than the root coordinate system. Coordinate conversions are performed between the source and target coordinates along branches extending from the source coordinate system to the common coordinate system and to the target coordinate system without returning to the root coordinate system. Contextual data is associated with the coordinates to permit conversion to an adjacent coordinate system. Since coordinate conversions are performed with respect to a common coordinate system, a distributed framework of coordinate systems is provided for reliably converting coordinates between source and target coordinate systems. New coordinate systems can be readily added to the tree.
摘要翻译：用于在源坐标系中的源坐标和目标坐标系中的目标坐标之间进行转换的方法包括定义从根坐标系延伸的坐标系转换树并分支到多个其它坐标系的步骤，包括源和目标坐标系，使得源和目标坐标系连接到除根坐标系以外的公共坐标系。在从源坐标系延伸到公共坐标系和目标坐标系的分支之间的源和目标坐标之间执行坐标转换，而不返回到根坐标系。上下文数据与坐标相关联，以允许转换到相邻坐标系。由于相对于公共坐标系执行坐标转换，所以提供了分布式坐标系框架，用于可靠地转换源坐标系和目标坐标系之间的坐标。新的坐标系可以轻松添加到树中。

6. 发明授权

US06763365B2 Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements 有权
标题翻译：使用多个几乎完全相同的处理器元件进行模数乘法的硬件实现
公开(公告)号：US06763365B2
公开(公告)日：2004-07-13
申请号：US09740685
申请日：2000-12-19
申请人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
发明人： Chin-Long Chen , Vincenzo Condorelli , Camil Fayad
IPC分类号： G06F738
CPC分类号： G06F7/728 , G06F7/721 , G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to the structure and linking of a plurality of almost identical processing elements.
摘要翻译：在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。虽然本公开涉及包括多个特征的复杂系统，但是本申请特别涉及多个几乎相同的处理元件的结构和链接。

7. 发明授权

US06757701B2 Apparatus and method for implementing a linearly approximated log map algorithm 有权
标题翻译：用于实现线性近似的对数映射算法的装置和方法
公开(公告)号：US06757701B2
公开(公告)日：2004-06-29
申请号：US09923007
申请日：2001-08-03
申请人： Noam Sivan , Fabrice Aidan , Gregory Leshin
发明人： Noam Sivan , Fabrice Aidan , Gregory Leshin
IPC分类号： G06F738
CPC分类号： H03M13/3911
摘要： A method and apparatus for implementing a linearly approximated Log MAP algorithm, the implementation involves calculating MAX*(a(n),b(n)) function, the method having the steps of: (A) Receiving a(n), b(n) and a value DE; (B) calculating (a(n)+b(n)+DE/2 and generating at least one intermediate result, the at least one intermediate result reflecting at least one relationship between at least two elements out of a(n), b(n) and DE; and (C) providing an MAX*(a(n),b(n)) result selected from a group comprising of a(n), b(n) or (a(n)+b(n)+DE)/2, the selection dependent upon the at least one intermediate result.
摘要翻译：一种用于实现线性近似Log MAP算法的方法和装置，该实现涉及计算MAX *（a（n），b（n））函数，该方法具有以下步骤：（A）接收a（n），b n）和值DE; （B）计算（a（n）+ b（n）+ DE / 2并生成至少一个中间结果，所述至少一个中间结果反映出a（n），b （n）和DE;以及（C）提供从包括a（n），b（n）或（a（n）+ b（n））的组中选择的MAX *（a（n），b n）+ DE）/ 2，选择取决于至少一个中间结果。

8. 发明授权

US06748412B2 Square-and-multiply exponent processor 有权
标题翻译：平方和倍数指数处理器
公开(公告)号：US06748412B2
公开(公告)日：2004-06-08
申请号：US09964137
申请日：2001-09-26
申请人： Michael D. Ruehle
发明人： Michael D. Ruehle
IPC分类号： G06F738
CPC分类号： G06F7/556
摘要： Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.
摘要翻译：使用平方和乘法技术处理指数，该方法在乘法阶段使用灵活的位数。可以在单次乘法运算中处理指数的多个位，从而减少将数字提高到指定功率所需的乘法运算的总数。通过检查除当前位之外的指数中的先前和后续位，可以将特定乘法运算中处理的位数量调整为指数中1和0的特定模式。

9. 发明授权

US06748410B1 Apparatus and method for modular multiplication and exponentiation based on montgomery multiplication 有权
标题翻译：基于montgomery乘法的乘法和乘法的装置和方法
公开(公告)号：US06748410B1
公开(公告)日：2004-06-08
申请号：US09480102
申请日：2000-01-10
申请人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
发明人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
IPC分类号： G06F738
CPC分类号： G06F7/728
摘要： This invention discloses apparatus and methods for accelerating processing, loading and unloading of data, from and to a plurality of memory addresses in a CPU having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.
摘要翻译：本发明公开了一种用于加速处理，加载和卸载数据的装置和方法，该装置和方法来自具有累加器的CPU中的多个存储器地址，以及用于连续整数计算的存储器映射协处理装置。

10. 发明授权

US06745220B1 Efficient exponentiation method and apparatus 失效
标题翻译：有效求幂法和装置
公开(公告)号：US06745220B1
公开(公告)日：2004-06-01
申请号：US09717895
申请日：2000-11-21
申请人： Laszlo Hars
发明人： Laszlo Hars
IPC分类号： G06F738
CPC分类号： G06F2207/7295
摘要： An encryption/decryption method performs an exponentiation operation on a base number where both the base number and the exponent may be large numbers (i.e., anywhere from 100 to several thousand bits long). The exponent is expressed as a bit string. The bit string is then re-coded utilizing the signed digit algorithm. Predetermined substring patterns are then extracted from the exponent utilizing a string replacement method and compared to a previously constructed look-up table containing exponent values for only a relatively small number of predetermined substrings. The value returned from the look-up table is the base value raised to the power represented by the substring. A pointer for each matching substring in the exponent is stored. The remaining bits in the exponent and intermediate values and are then processed with the base value using a multiply chain algorithm to determine the value of the base raised to the exponent.
摘要翻译：加密/解密方法对基数执行取幂运算，其中基数和指数都可以是大数（即，从100到几千比特长的任何地方）。指数表示为位串。然后使用有符号位算法重新编码位串。然后使用字符串替换方法从指数中提取预定的子字符串模式，并与仅包含相对较少数量的预定子字符串的指数值的先前构造的查找表进行比较。从查找表返回的值是由子字符串表示的幂的基值。存储指数中每个匹配子字符串的指针。指数和中间值中的其余位，然后使用乘法运算法使用基值进行处理，以确定提升到指数的基数值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式