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1. 发明授权

US07281136B2 LSI design method and verification method 有权
标题翻译： LSI设计方法和验证方法
公开(公告)号：US07281136B2
公开(公告)日：2007-10-09
申请号：US09779440
申请日：2001-02-09
申请人： Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
发明人： Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
IPC分类号： G06F12/14 , G06F17/50
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
摘要翻译：在LSI设计中采用加密处理，以便改进电路设计数据对传统示例的保密性。在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。将加密的设计数据提供给进行设计/验证处理的用户。钥匙也按要求提供。在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。

2. 发明授权

US5459049A Motilin-like polypeptide and use thereof 失效
标题翻译：胃动素样多肽及其用途
公开(公告)号：US5459049A
公开(公告)日：1995-10-17
申请号：US3688
申请日：1993-01-13
申请人： Masayasu Kurono , Takahiko Matani , Haruo Takahashi , Kenichi Tanaka , Katsuya Fujimura , Yuji Hayashi , Yohei Kobayashi , Kiichi Sawai
发明人： Masayasu Kurono , Takahiko Matani , Haruo Takahashi , Kenichi Tanaka , Katsuya Fujimura , Yuji Hayashi , Yohei Kobayashi , Kiichi Sawai
IPC分类号： A61K38/00 , C07K14/63 , C12N15/16 , C12N15/63 , C12N15/67
CPC分类号： C07K14/63 , A61K38/00 , C07K2319/02
摘要： A process for the preparation of a polypeptide of the formula ##STR1## wherein A' is Pro, Gly, Asp or Ser; B' is Gly, Asn or Ser; C is Gln, Glu or Asp; D is Asn, Glu or Asp; X' is a residue of amino acid other than Met; E is Gln, Lys or Arg, and Y' is a residue of homoserine or homoserine-lactone, as well as a recombinant DNA and expression plasmid for preparing the polypeptide.
摘要翻译：制备式Phe-Val-A'-Ile-Phe-Thr-Tyr-B'-Glu-Leu-C-TR-Arg-X'-Gln-Glu-Lys-Glu的多肽的方法 -Arg-D-Lys-Gly-EY'，其中A'为Pro，Gly，Asp或Ser; B'是Gly，Asn或Ser; C是Gln，Glu或Asp; D是Asn，Glu或Asp; X'是Met以外的氨基酸残基; E是Gln，Lys或Arg，Y'是高丝氨酸或高丝氨酸 - 内酯的残基，以及用于制备多肽的重组DNA和表达质粒。

3. 发明申请

US20070038908A1 Design data structure for semiconductor integrated circuit and apparatus and method for designing the same 审中-公开
标题翻译：半导体集成电路的设计数据结构及其设计及其设计方法
公开(公告)号：US20070038908A1
公开(公告)日：2007-02-15
申请号：US11378396
申请日：2006-03-20
申请人： Yoko Hirano , Katsuya Fujimura , Aya Mototani , Sadami Takeoka
发明人： Yoko Hirano , Katsuya Fujimura , Aya Mototani , Sadami Takeoka
IPC分类号： G01R31/28
CPC分类号： G01R31/31704 , G01R31/31701 , G01R31/3172
摘要： Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of the design data and, after the code analysis, the resulting design data is stored by a database storage unit in a storage device. A test point deletion unit receives the test mode specified from the outside and deletes data on an unnecessary test point from the design data stored in the storage device. The design data which does not include the unnecessary test point is outputted from a data output unit. Accordingly, even when the test mode is changed, there is no need to calculate the test efficiency again in response to each change or add the step of inserting a new test point.
摘要翻译：包括测试点的电路数据的设计数据和已经附加到测试点的测试模式的信息被输入到用于设计半导体集成电路的设备。数据输入单元中的设计数据代码分析单元执行设计数据的代码分析，并且在代码分析之后，所得到的设计数据由数据库存储单元存储在存储设备中。测试点删除单元接收从外部指定的测试模式，并从存储在存储设备中的设计数据中删除不必要的测试点上的数据。不包括不必要的测试点的设计数据从数据输出单元输出。因此，即使在变更了测试模式的情况下，也不需要根据每次变更再次计算测试效率，或者添加插入新的测试点的步骤。

4. 发明申请

US20070011468A1 LSI design method and verification method 审中-公开
公开(公告)号：US20070011468A1
公开(公告)日：2007-01-11
申请号：US11520712
申请日：2006-09-14
申请人： Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
发明人： Kentaro Shiomi , Akira Motohara , Makoto Fujiwara , Toshiyuki Yokoyama , Katsuya Fujimura
IPC分类号： G06F12/14
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

5. 发明授权

US07148503B2 Semiconductor device, function setting method thereof, and evaluation method thereof 有权
公开(公告)号：US07148503B2
公开(公告)日：2006-12-12
申请号：US09968898
申请日：2001-10-03
申请人： Katsuya Fujimura , Toshiyuki Yokoyama , Kentaro Shiomi , Akira Motohara
发明人： Katsuya Fujimura , Toshiyuki Yokoyama , Kentaro Shiomi , Akira Motohara
IPC分类号： H01L23/58 , H01L29/10 , H01L29/00
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

6. 发明申请

US20060275932A1 Semiconductor device, function setting method thereof, and evaluation method thereof 审中-公开
公开(公告)号：US20060275932A1
公开(公告)日：2006-12-07
申请号：US11496574
申请日：2006-08-01
申请人： Katsuya Fujimura , Toshiyuki Yokoyama , Kentaro Shiomi , Akira Motohara
发明人： Katsuya Fujimura , Toshiyuki Yokoyama , Kentaro Shiomi , Akira Motohara
IPC分类号： H01L21/00
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

7. 发明申请

US20050086621A1 Method for processing design data of semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计数据处理方法
公开(公告)号：US20050086621A1
公开(公告)日：2005-04-21
申请号：US10895821
申请日：2004-07-22
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , H01L21/82
CPC分类号： G06F17/5045
摘要： A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.
摘要翻译：显示缓冲器和逆变器在不改变逻辑的情况下被去除的电路。这种电路是通过第一种或第二种方法获得的。利用第一种方法，不改变逻辑的所有缓冲器，并且当在布线的分支点处划分时钟路径时，位于每个划分时钟路径上的所有反相器对都从时钟电路中去除。利用第二种方法，将位于多个时钟路径上的逻辑元件复制并添加到时钟电路中，除去不改变逻辑的所有缓冲器和位于除了上述缓冲器之外的逻辑元件之间的所有反相器对，并且冗余去除实现相同逻辑并位于多个时钟路径上的部分电路（如果有的话）。因此，可以显示时钟电路，以便于设计者对逻辑的理解。

8. 发明申请

US20050060676A1 Semiconductor integrated circuit and method for designing same 审中-公开
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20050060676A1
公开(公告)日：2005-03-17
申请号：US10817959
申请日：2004-04-06
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F1/10 , G06F9/45 , G06F17/50 , H01L21/82 , H03L7/06
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
摘要翻译：本发明提供一种半导体集成电路，其中即使存在制造变异性，也不可能发生定时误差。分别包括在第一和第二时钟电路11和12中的逻辑单元16和17由均匀尺寸的晶体管形成。即使存在制造变化，第一时钟电路11的延迟时间t1和第二时钟电路12的延迟时间t2增加或减少相同的时间量。因此，在第二触发器15中不可能发生定时误差。每个时钟单元中包括的逻辑单元可以由具有均匀矩形扩散区域的晶体管形成。

9. 发明授权

US5578456A Anti-treponema pallidum antibody immunoassay 失效
标题翻译：抗梅毒螺旋体抗体免疫测定
公开(公告)号：US5578456A
公开(公告)日：1996-11-26
申请号：US395507
申请日：1995-02-27
申请人： Katsuya Fujimura , Eiichi Ueno , Nobuyuki Fujii , Masahisa Okada
发明人： Katsuya Fujimura , Eiichi Ueno , Nobuyuki Fujii , Masahisa Okada
IPC分类号： C07K14/20 , G01N33/571
CPC分类号： C07K14/20 , G01N33/571 , C07K2319/00 , Y10S436/811
摘要： A new method for assaying anti-Treponema pallidum antibody with improved sensitivity is provided. Anti-Tp antibody in serum is assayed by enzyme immunoanalysis utilizing the antigen-antibody reaction between G15 and/or G17 antigen, a protein available on fusion of GST to the N-terminal of a Tp membrane antigen (15 and/or 17 kDa), and anti-Tp antibody in a sample.
摘要翻译：提供了一种用于测定灵敏度提高的抗梅毒螺旋体抗体的新方法。使用G15和/或G17抗原之间的抗原 - 抗体反应通过酶免疫分析来测定血清中的抗Tp抗体，G15和/或G17抗原是GST与Tp膜抗原（15和/或17kDa）的N端融合时可获得的蛋白质。，和抗Tp抗体。

10. 发明申请

US20080141202A1 Semiconductor integrated circuit and method of designing the same 审中-公开
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20080141202A1
公开(公告)日：2008-06-12
申请号：US12007413
申请日：2008-01-10
申请人： Yoichi MATSUMURA , Takako OHASHI , Katsuya FUJIMURA , Chihiro ITOH , Hiroki TANIGUCHI
发明人： Yoichi MATSUMURA , Takako OHASHI , Katsuya FUJIMURA , Chihiro ITOH , Hiroki TANIGUCHI
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
摘要翻译：在半导体集成电路中，由于电源线中包含电阻成分，所以提供给时钟路径上的单元的电源电压下降，造成时钟偏移。为了避免这个问题，以时钟路径上的单元10为中心设置单元放置禁止区域，在该单元放置禁止区域中不设置用于执行逻辑运算的单元。此外，可以为由紧密放置在一起的多个单元形成的每个单元组设置单元布置禁止区域。此外，可以将电容单元放置在电池放置禁止区域中。

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