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1. 发明申请

US20060197573A1 Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路及半导体集成电路制造方法
公开(公告)号：US20060197573A1
公开(公告)日：2006-09-07
申请号：US11365604
申请日：2006-03-02
申请人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
发明人： Yoichi Matsumura , Takako Ohashi , Fumihiro Kimura , Kiyohito Mukai , Masanori Itou
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G01R31/2856
摘要： The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.
摘要翻译：本发明的半导体集成电路包括用于产生时钟信号的时钟电路。时钟电路包括用于控制时钟信号传播的时钟控制电路。该时钟控制电路包括一个老化控制信号输入端，用于输入一个控制时钟电路在进行老化处理时的运行状态的老化控制信号，以及一个用于输出时钟信号的时钟控制信号输出端。时钟控制电路基于输入到老化控制信号输入端子的老化控制信号，控制从时钟控制信号输出端子输出的时钟信号的传播。

2. 发明授权

US08487423B2 Interconnect structure of semiconductor integrated circuit and semiconductor device including the same 有权
标题翻译：半导体集成电路的互连结构和包括其的半导体器件
公开(公告)号：US08487423B2
公开(公告)日：2013-07-16
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

3. 发明申请

US20110260333A1 INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：半导体集成电路和包括其中的半导体器件的互连结构
公开(公告)号：US20110260333A1
公开(公告)日：2011-10-27
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

4. 发明授权

US07334210B2 Semiconductor integrated circuit and method of designing the same 有权
公开(公告)号：US07334210B2
公开(公告)日：2008-02-19
申请号：US10980269
申请日：2004-11-04
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

5. 发明申请

US20070252258A1 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US20070252258A1
公开(公告)日：2007-11-01
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： H01L23/02 , G08B13/14 , H01Q9/04
CPC分类号： H01L27/0203 , H01L27/118
摘要： In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
摘要翻译：在形成连接到栅极的布线的每个布线层中，布线被布线成不覆盖天线保护元件的有源区。形成在上布线层中的布线被布线以覆盖天线保护元件的有源区域的至少一部分。

6. 发明申请

US20050097492A1 Semiconductor integrated circuit and method of designing the same 有权
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20050097492A1
公开(公告)日：2005-05-05
申请号：US10980269
申请日：2004-11-04
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50 , G06F9/45 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
摘要翻译：在半导体集成电路中，由于电源线中包含电阻成分，所以提供给时钟路径上的单元的电源电压下降，造成时钟偏移。为了避免这个问题，以时钟路径上的单元10为中心设置单元放置禁止区域，在该单元放置禁止区域中不设置用于执行逻辑运算的单元。此外，可以为由紧密放置在一起的多个单元形成的每个单元组设置单元布置禁止区域。此外，可以将电容单元放置在电池放置禁止区域中。

7. 发明申请

US20090193374A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGNING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：设计半导体集成电路器件，设计器件和半导体集成电路器件的方法
公开(公告)号：US20090193374A1
公开(公告)日：2009-07-30
申请号：US12352206
申请日：2009-01-12
申请人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
发明人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5031 , H01L24/02 , H01L2924/01004 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.
摘要翻译：作为考虑由衬垫引起的应力的不利影响的方法，提供了两种方法。作为一种方法，当计算由应力的不利影响引起的电池的延迟变化值时，将所计算的延迟变化值应用于电池，以便通过考虑应力的不利影响进行定时分析等。然后，为了通过采用上述分析的结果来设计倒装芯片型LSI，使得不会对由焊盘施加的应力的不利影响赋予位于下面的通孔，布线和电池采用垫，这样的物理结构，没有通孔布置在垫下方。

8. 发明申请

US20050086621A1 Method for processing design data of semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计数据处理方法
公开(公告)号：US20050086621A1
公开(公告)日：2005-04-21
申请号：US10895821
申请日：2004-07-22
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , H01L21/82
CPC分类号： G06F17/5045
摘要： A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.
摘要翻译：显示缓冲器和逆变器在不改变逻辑的情况下被去除的电路。这种电路是通过第一种或第二种方法获得的。利用第一种方法，不改变逻辑的所有缓冲器，并且当在布线的分支点处划分时钟路径时，位于每个划分时钟路径上的所有反相器对都从时钟电路中去除。利用第二种方法，将位于多个时钟路径上的逻辑元件复制并添加到时钟电路中，除去不改变逻辑的所有缓冲器和位于除了上述缓冲器之外的逻辑元件之间的所有反相器对，并且冗余去除实现相同逻辑并位于多个时钟路径上的部分电路（如果有的话）。因此，可以显示时钟电路，以便于设计者对逻辑的理解。

9. 发明申请

US20050060676A1 Semiconductor integrated circuit and method for designing same 审中-公开
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20050060676A1
公开(公告)日：2005-03-17
申请号：US10817959
申请日：2004-04-06
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F1/10 , G06F9/45 , G06F17/50 , H01L21/82 , H03L7/06
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
摘要翻译：本发明提供一种半导体集成电路，其中即使存在制造变异性，也不可能发生定时误差。分别包括在第一和第二时钟电路11和12中的逻辑单元16和17由均匀尺寸的晶体管形成。即使存在制造变化，第一时钟电路11的延迟时间t1和第二时钟电路12的延迟时间t2增加或减少相同的时间量。因此，在第二触发器15中不可能发生定时误差。每个时钟单元中包括的逻辑单元可以由具有均匀矩形扩散区域的晶体管形成。

10. 发明授权

US08028264B2 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US08028264B2
公开(公告)日：2011-09-27
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , H01L27/118
摘要： A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
摘要翻译：一种半导体器件，包括具有天线保护元件和除天线保护元件之外的单元的多个单元; 以及布置在所述多个单元上方的层中的第一虚设图案和第二虚设图案。此外，第一伪图案与天线保护元件重叠，第二虚设图案与天线保护元件以外的单元重叠，并且第一虚设图案的第一布局规则与第二虚设图案的第二布局规则不同。

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