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1. 发明授权

US08582381B2 Temperature based compensation during verify operations for non-volatile storage 有权
标题翻译：用于非易失性存储的验证操作期间的温度补偿
公开(公告)号：US08582381B2
公开(公告)日：2013-11-12
申请号：US13403934
申请日：2012-02-23
申请人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
发明人： Ken Oowada , Yingda Dong , Gerrit Jan Hemink , Man Lung Mui , Hao Nguyen , Seungpil Lee , Jong Park , Fanglin Zhang
IPC分类号： G11C7/04 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/06 , G11C7/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/34 , G11C16/3454 , G11C16/3459 , G11C16/3481 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.
摘要翻译：执行编程和读取过程的非易失性存储系统。编程过程包括粗/精编程和验证操作。通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得两个有效的测试阈值电压水平在温度变化上保持恒定。

2. 发明申请

US20110026331A1 PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY 有权
标题翻译：程序电压补偿与字线偏置更改为在存储器中禁止充电捕获
公开(公告)号：US20110026331A1
公开(公告)日：2011-02-03
申请号：US12512181
申请日：2009-07-30
申请人： Yingda Dong , Toru Ishigaki , Ken Oowada
发明人： Yingda Dong , Toru Ishigaki , Ken Oowada
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3404
摘要： Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.
摘要翻译：在所选择的字线的编程操作期间，在非易失性存储系统中，通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。这有助于减少浮栅边缘的电荷捕获，这可以通过增加编程擦除周期来扩大阈值电压分布。当将较高幅度的编程脉冲施加到所选字线时，通过电压切换到较高电平以提供足够量的通道升压。可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。当通过电压升高时，编程电压的幅度降低，从通过电压的变化中消除所选存储元件的电容耦合。

3. 发明申请

US20090296475A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20090296475A1
公开(公告)日：2009-12-03
申请号：US12132452
申请日：2008-06-03
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

4. 发明申请

US20080279008A1 NON-VOLATILE STORAGE WITH BOOSTING USING CHANNEL ISOLATION SWITCHING 有权
标题翻译：使用通道隔离开关进行升压的非易失性存储
公开(公告)号：US20080279008A1
公开(公告)日：2008-11-13
申请号：US11745092
申请日：2007-05-07
申请人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
发明人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： Non-volatile storage in which program disturb is reduced by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：通过防止所选择的NAND串中的源极升压来减少编程干扰的非易失性存储。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

5. 发明授权

US07447086B2 Selective program voltage ramp rates in non-volatile memory 有权
标题翻译：非易失性存储器中的选择性编程电压斜坡率
公开(公告)号：US07447086B2
公开(公告)日：2008-11-04
申请号：US11866261
申请日：2007-10-02
申请人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
发明人： Jun Wan , Jeffrey Lutze , Masaaki Higashitani , Gerrit Jan Hemink , Ken Oowada , Jian Chen , Geoffrey S Gongwer
IPC分类号： G11C7/00
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择程序禁止方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

6. 发明授权

US07355888B2 Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages 有权
标题翻译：用于使用改进的通过电压来减少编程干扰来编程非易失性存储器的装置
公开(公告)号：US07355888B2
公开(公告)日：2008-04-08
申请号：US11312925
申请日：2005-12-19
申请人： Gerrit Jan Hemink , Ken Oowada
发明人： Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/565
摘要： Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.
摘要翻译：非易失性存储元件以通过使用修改的通过电压来减少编程干扰的方式进行编程。特别地，在与所选择的字线相关联的所选择的存储元件的编程期间，将较高的通过电压施加到与组中的先前编程的非易失性存储元件相关联的字线，而不是与未编程和/或部分相关联的字线在集合中编程的非易失性存储元件。通过电压足够高以平衡所选字线的源极和漏极侧上的沟道电位和/或减小在升压的沟道区之间的电荷泄漏。可选地，通过在所选择的字线和接收较高通过电压的字线之间的一个或多个字线上施加降低的电压，在升压的沟道区之间形成隔离区。

7. 发明授权

US08811091B2 Non-volatile memory and method with improved first pass programming 有权
标题翻译：非易失性存储器和具有改进的第一遍编程的方法
公开(公告)号：US08811091B2
公开(公告)日：2014-08-19
申请号：US13329103
申请日：2011-12-16
申请人： Yan Li , Cynthia Hsu , Ken Oowada
发明人： Yan Li , Cynthia Hsu , Ken Oowada
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3468
摘要： A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.
摘要翻译：具有多遍编程方案的非易失性存储器使得能够以降低的浮栅到浮栅扰动（Yuping效应）来编程一页多层存储单元。存储器单元在公共阈值电压范围或窗口内工作，其被划分为多个频带以表示一系列日益编程的状态。该系列分为两部分，一组较低，一组较高。存储器单元被编程在第一粗略编程遍历中，使得具有来自较高集合的目标状态的页面的存储器单元被编程到阈值窗口中途附近的分段区域。特别地，它们被编程为比先前的方案更接近目标目的地，而不会导致太多的性能损失。随后的通行证将更快地完成编程。 Yuping效应降低，因为后续通过中的阈值电压变化减小。

8. 发明授权

US08472257B2 Nonvolatile memory and method for improved programming with reduced verify 有权
标题翻译：非易失性存储器和方法，通过减少验证来改进编程
公开(公告)号：US08472257B2
公开(公告)日：2013-06-25
申请号：US13071170
申请日：2011-03-24
申请人： Yingda Dong , Ken Oowada , Cynthia Hsu
发明人： Yingda Dong , Ken Oowada , Cynthia Hsu
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
摘要翻译：非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。存储器状态由一组增加的分界阈值（V1，...，VN）划分。最初在编程过程中，相对于测试参考阈值验证存储器单元。该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

9. 发明申请

US20110235423A1 VERIFICATION PROCESS FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：US20110235423A1
公开(公告)日：2011-09-29
申请号：US13154810
申请日：2011-06-07
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

10. 发明授权

US07995394B2 Program voltage compensation with word line bias change to suppress charge trapping in memory 有权
标题翻译：程序电压补偿用字线偏置改变，以抑制存储器中的电荷捕获
公开(公告)号：US07995394B2
公开(公告)日：2011-08-09
申请号：US12512181
申请日：2009-07-30
申请人： Yingda Dong , Toru Ishigaki , Ken Oowada
发明人： Yingda Dong , Toru Ishigaki , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3404
摘要： Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.
摘要翻译：在所选择的字线的编程操作期间，在非易失性存储系统中，通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。这有助于减少浮栅边缘的电荷捕获，这可以通过增加编程擦除周期来扩大阈值电压分布。当将较高幅度的编程脉冲施加到所选字线时，通过电压切换到较高电平以提供足够量的通道升压。可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。当通过电压升高时，编程电压的幅度降低，从通过电压的变化中消除所选存储元件的电容耦合。

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