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1. 发明授权

US07992020B1 Power management with packaged multi-die integrated circuit 有权
标题翻译：电源管理与封装的多芯片集成电路
公开(公告)号：US07992020B1
公开(公告)日：2011-08-02
申请号：US12043096
申请日：2008-03-05
申请人： Tim Tuan , Kerry M. Pierce , Albert Franceschino
发明人： Tim Tuan , Kerry M. Pierce , Albert Franceschino
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.
摘要翻译：描述了使用封装的多芯片集成电路（IC）进行电源管理。第一集成电路管芯能够具有第一操作模式。第二集成电路管芯耦合到第一集成电路管芯。当第一集成电路管芯处于第一操作模式并且第二集成电路管芯处于第二操作模式时，第一集成电路管芯具有低于第二集成电路管芯的功率消耗率。第一集成电路管芯被配置为用于第二集成电路管芯的电源管理，用于将第二集成电路管芯从第二操作模式放置在待机模式中，并且用于将第二集成电路管芯退回到从待机模式的第二操作模式。

2. 发明授权

US5646564A Phase-locked delay loop for clock correction 失效
标题翻译：用于时钟校正的锁相延迟环
公开(公告)号：US5646564A
公开(公告)日：1997-07-08
申请号：US632523
申请日：1996-04-12
申请人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
发明人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
IPC分类号： G06F1/10 , H03K5/15 , H03L7/081 , H03L7/085 , H03L7/00 , H03K5/00
CPC分类号： H03L7/0812 , G06F1/10 , H03K5/1504 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.
摘要翻译：受控的延迟路径将选定的延迟插入到时钟分配电路中以产生等于相对于参考输入时钟信号的整数个时钟周期的总时钟延迟，或者产生与参考时钟信号的选择的相位关系。本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。参考输入时钟信号通过接收参考输入时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。可以包括额外的可选择的延迟，其创建偏移选项并允许选择引导，滞后或同相参考输入时钟/输出时钟关系。在本发明的一种形式中，适用于反转参考输入时钟和输出时钟信号之一的发明者，以及用于降低时钟频率的N电路的除法，同时大致调整延迟。

3. 发明授权

US5319252A Load programmable output buffer 失效
标题翻译：加载可编程输出缓冲区
公开(公告)号：US5319252A
公开(公告)日：1994-06-07
申请号：US973365
申请日：1992-11-05
申请人： Kerry M. Pierce , Roger D. Carpenter
发明人： Kerry M. Pierce , Roger D. Carpenter
IPC分类号： G05F3/24 , G05F1/565 , H03K17/16 , G05F3/08 , H03K5/12
CPC分类号： G05F1/565 , H03K17/166 , H03K17/167
摘要： The present invention reduces bounce in the power or ground supply voltages of an integrated circuit chip by gradually turning output drivers both on and off, so there is not a sharp discontinuity in current flow to an external device. Greatest current flow occurs at the middle of a transition period. The gradual turn-off at the end of a transition is achieved by feeding back voltage of the output signal to a device which controls the output driver. As output voltage approaches its final value, the output driver gradually turns off, preventing a sharp transient in the power or ground voltage of the integrated circuit chip.
摘要翻译：本发明通过逐渐地将输出驱动器打开和关闭来减少集成电路芯片的电源或接地电源电压的反弹，因此当前流向外部设备的电流没有明显的不连续性。最大电流在过渡期的中间发生。通过将输出信号的电压反馈到控制输出驱动器的装置来实现转换结束时的逐渐关断。当输出电压接近其最终值时，输出驱动器逐渐关闭，防止集成电路芯片的电源或接地电压发生急剧的瞬变。

4. 发明授权

US5801546A Interconnect architecture for field programmable gate array using variable length conductors 失效
公开(公告)号：US5801546A
公开(公告)日：1998-09-01
申请号：US667571
申请日：1996-06-21
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

5. 发明授权

US5760604A Interconnect architecture for field programmable gate array 失效
标题翻译：现场可编程门阵列的互连架构
公开(公告)号：US5760604A
公开(公告)日：1998-06-02
申请号：US656752
申请日：1996-06-03
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

6. 发明授权

US5481206A Circuit for fast carry and logic 失效
标题翻译：快速进位和逻辑电路
公开(公告)号：US5481206A
公开(公告)日：1996-01-02
申请号：US310113
申请日：1994-09-20
申请人： Bernard J. New , Kerry M. Pierce
发明人： Bernard J. New , Kerry M. Pierce
IPC分类号： G06F7/38 , G06F7/00 , G06F7/50 , G06F7/503 , G06F7/506 , G06F7/507 , G06F7/57 , H03K19/173 , H03K19/177 , H03K19/20
CPC分类号： G06F7/507 , G06F7/503 , H03K19/1737 , G06F2207/4812
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.
摘要翻译：使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。该电路包括允许快速携带硬件执行附加常用功能的附加结构。

7. 发明授权

US5146306A Semiconductor FET structures with slew-rate control 失效
标题翻译：具有转换速率控制的半导体FET结构
公开(公告)号：US5146306A
公开(公告)日：1992-09-08
申请号：US638629
申请日：1991-01-08
申请人： Thomas V. Ferry , Jamil Kawa , Kerry M. Pierce , William G. Walker , James S. Hsue
发明人： Thomas V. Ferry , Jamil Kawa , Kerry M. Pierce , William G. Walker , James S. Hsue
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates. Further control of the delay is gained by use of a feedback signal to increase or decrease the current in the gates.
摘要翻译：在使用MOSFET来切换输出信号的输入/输出器件结构中实现压摆率控制。这些MOSFET各自具有基板，与基板相邻的绝缘层和通过绝缘层与基板分离的半导体材料条。半导体材料条作为MOSFET的栅极起作用。半导体材料条不形成闭环。第一晶体管的条的一端连接到第二晶体管的条的一端。因此，两个晶体管的栅极被串联放置，使得它们不被同时接通。因此在两个晶体管的接通之间自动引入延迟。通过将金属带放置在选定的晶体管栅极上来有效地绕过由栅极传播的电流引起的延迟来控制延迟。通过使用反馈信号来增加或减少门中的电流来获得延迟的进一步控制。

8. 发明授权

US08099564B1 Programmable memory controller 有权
标题翻译：可编程存储控制器
公开(公告)号：US08099564B1
公开(公告)日：2012-01-17
申请号：US11891378
申请日：2007-08-10
申请人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
发明人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.
摘要翻译：在可编程集成电路中实现的存储器控制器可以包括具有命令寄存器和多个数据先进先出（FIFO）存储器的用户接口，其中命令寄存器可以接收数据FIFO存储器的地址多个数据FIFO存储器。耦合到用户界面的核心控制器可以响应于来自用户界面的指令来生成控制信号，该控制信号在耦合到核心控制器的存储器设备内启动操作。与核心控制器，用户界面和存储设备耦合的物理层可以响应于存储器设备的读取操作，根据在命令中接收的地址存储从所选择的数据FIFO存储器中的存储器设备接收的数据寄存器。

9. 发明授权

US5489858A Soft wakeup output buffer 失效
标题翻译：软唤醒输出缓冲区
公开(公告)号：US5489858A
公开(公告)日：1996-02-06
申请号：US246048
申请日：1994-05-19
申请人： Kerry M. Pierce , Charles R. Erickson
发明人： Kerry M. Pierce , Charles R. Erickson
IPC分类号： H03K19/173 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/00361
摘要： Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要翻译：当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时，电源或接地电压可能会波动。特别是在输出缓冲器的全局高阻抗状态释放之后，其中输出信号被被动地驱动到选择的逻辑状态。为了防止电源和接地电压变化，缓冲器具有用于以慢响应（高偏移）模式操作的装置。压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。当转换速率控制电路接收到结束缓冲器的高阻状态的信号时，对该信号施加延迟，并且在延迟时间允许缓冲器移动到快速响应模式之后。当高电容端子移动到新的逻辑状态时，慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。

10. 发明授权

US5581199A Interconnect architecture for field programmable gate array using variable length conductors 失效
标题翻译：使用可变长度导体的现场可编程门阵列的互连架构
公开(公告)号：US5581199A
公开(公告)日：1996-12-03
申请号：US368692
申请日：1995-01-04
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

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