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1. 发明授权

US5489858A Soft wakeup output buffer 失效
标题翻译：软唤醒输出缓冲区
公开(公告)号：US5489858A
公开(公告)日：1996-02-06
申请号：US246048
申请日：1994-05-19
申请人： Kerry M. Pierce , Charles R. Erickson
发明人： Kerry M. Pierce , Charles R. Erickson
IPC分类号： H03K19/173 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/00361
摘要： Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要翻译：当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时，电源或接地电压可能会波动。特别是在输出缓冲器的全局高阻抗状态释放之后，其中输出信号被被动地驱动到选择的逻辑状态。为了防止电源和接地电压变化，缓冲器具有用于以慢响应（高偏移）模式操作的装置。压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。当转换速率控制电路接收到结束缓冲器的高阻状态的信号时，对该信号施加延迟，并且在延迟时间允许缓冲器移动到快速响应模式之后。当高电容端子移动到新的逻辑状态时，慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。

2. 发明授权

US5801546A Interconnect architecture for field programmable gate array using variable length conductors 失效
公开(公告)号：US5801546A
公开(公告)日：1998-09-01
申请号：US667571
申请日：1996-06-21
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

3. 发明授权

US5760604A Interconnect architecture for field programmable gate array 失效
标题翻译：现场可编程门阵列的互连架构
公开(公告)号：US5760604A
公开(公告)日：1998-06-02
申请号：US656752
申请日：1996-06-03
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

4. 发明授权

US5581199A Interconnect architecture for field programmable gate array using variable length conductors 失效
标题翻译：使用可变长度导体的现场可编程门阵列的互连架构
公开(公告)号：US5581199A
公开(公告)日：1996-12-03
申请号：US368692
申请日：1995-01-04
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

5. 发明授权

US5331220A Soft wakeup output buffer 失效
标题翻译：软唤醒输出缓冲区
公开(公告)号：US5331220A
公开(公告)日：1994-07-19
申请号：US016643
申请日：1993-02-12
申请人： Kerry M. Pierce , Charles R. Erickson
发明人： Kerry M. Pierce , Charles R. Erickson
IPC分类号： H03K19/173 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/092 , H03K19/00
CPC分类号： H03K19/00361
摘要： Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要翻译：当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时，电源或接地电压可能会波动。特别是在输出缓冲器的全局高阻抗状态释放之后，其中输出信号被被动地驱动到选择的逻辑状态。为了防止电源和接地电压变化，缓冲器具有用于以慢响应（高转换）模式操作的装置。压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。当转换速率控制电路接收到结束缓冲器的高阻状态的信号时，对该信号施加延迟，并且在延迟时间允许缓冲器移动到快速响应模式之后。当高电容端子移动到新的逻辑状态时，慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。

6. 发明授权

US5646564A Phase-locked delay loop for clock correction 失效
标题翻译：用于时钟校正的锁相延迟环
公开(公告)号：US5646564A
公开(公告)日：1997-07-08
申请号：US632523
申请日：1996-04-12
申请人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
发明人： Charles R. Erickson , Philip M. Freidin , Kerry M. Pierce
IPC分类号： G06F1/10 , H03K5/15 , H03L7/081 , H03L7/085 , H03L7/00 , H03K5/00
CPC分类号： H03L7/0812 , G06F1/10 , H03K5/1504 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.
摘要翻译：受控的延迟路径将选定的延迟插入到时钟分配电路中以产生等于相对于参考输入时钟信号的整数个时钟周期的总时钟延迟，或者产生与参考时钟信号的选择的相位关系。本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。参考输入时钟信号通过接收参考输入时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。可以包括额外的可选择的延迟，其创建偏移选项并允许选择引导，滞后或同相参考输入时钟/输出时钟关系。在本发明的一种形式中，适用于反转参考输入时钟和输出时钟信号之一的发明者，以及用于降低时钟频率的N电路的除法，同时大致调整延迟。

7. 发明授权

US5815016A Phase-locked delay loop for clock correction 失效
标题翻译：用于时钟校正的锁相延迟环
公开(公告)号：US5815016A
公开(公告)日：1998-09-29
申请号：US665169
申请日：1996-06-14
申请人： Charles R. Erickson
发明人： Charles R. Erickson
IPC分类号： G06F1/10 , H03L7/081 , H03L7/085 , H03L7/00 , H03K5/00
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.
摘要翻译：受控的延迟路径将选定的延迟插入到时钟分配电路中，以创建等于相对于参考停靠信号的整数个时钟周期的总时钟延迟，或者产生与参考停靠信号的选择的相位关系。本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。参考时钟信号通过接收参考时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生一个误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。可以包括额外的可选择的延迟，其创建偏移选项并且允许选择引导，滞后或同相参考停靠/输出时钟关系。在一个实施例中，时钟信号的正和负边缘都被校正。作为另一个特征，如果校正始终在相同的方向上，则产生错误标志。

8. 发明授权

US5789938A Structure and method for reading blocks of data from selectable points in a memory device 失效
公开(公告)号：US5789938A
公开(公告)日：1998-08-04
申请号：US707545
申请日：1996-09-04
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

9. 发明授权

US5694056A Fast pipeline frame full detector 失效
标题翻译：快速管线框架全检测器
公开(公告)号：US5694056A
公开(公告)日：1997-12-02
申请号：US627815
申请日：1996-04-01
申请人： John E. Mahoney , Stephen M. Trimberger , Charles R. Erickson
发明人： John E. Mahoney , Stephen M. Trimberger , Charles R. Erickson
IPC分类号： H03K19/177
CPC分类号： H03K19/17704
摘要： A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration data into the IC. Therefore, the present invention advantageously reduces this limiting factor.
摘要翻译：一条流水线全检测电路。本发明可以在使用串行数据流和传送机制将配置数据加载到集成电路（IC）的系统中操作。对于给定的IC，配置数据以指定大小的连续帧传送到IC。配置数据的第一位包含一个帧完整指示符。配置数据被传送到移位寄存器电路中，并且除了存储在移位寄存器电路之外，移位寄存器电路的最后位位置沿特殊帧完整流水线移动到控制单元。控制单元在检测到帧全指示符时，断言并行写入命令，使得移位寄存器电路的数据被并行地传送到存储器的接收列。复位信号后，新的配置数据可以被串行移位到相同的移位寄存器电路中。通过将帧满指示符移动通过流水线，帧全指示器到达控制单元所需的传播延迟显着降低。正是这种传播延迟将配置数据的传输速率限制在IC中。因此，本发明有利地减少了这个限制因素。

10. 发明授权

US5613099A Persistent object storage system with modifiable group skeletal formats 失效
标题翻译：具有可修改的组骨架格式的持久对象存储系统
公开(公告)号：US5613099A
公开(公告)日：1997-03-18
申请号：US409109
申请日：1995-03-23
申请人： Charles R. Erickson , Roger H. Sessions
发明人： Charles R. Erickson , Roger H. Sessions
IPC分类号： G06F9/44 , G06F7/00
CPC分类号： G06F9/4435
摘要： A system of modifiable group skeletal formatting of persistent objects. The object oriented framework provides abstract classes for persistent object grouping and storage. Abstract classes define the interfaces and allow implementation details to be deferred until runtime. The implementor creates subclasses overriding the abstract methods and implementing specific group skeletal formats. Multiple formats can be defined and object instance variables set to indicate which formatter to use. The defined interfaces and methods allows interchangeable substitution of group formatters.
摘要翻译：持久性对象的可修改组骨架格式化系统。面向对象的框架为持久对象分组和存储提供了抽象类。抽象类定义接口并允许实现细节被延迟到运行时。实现者创建覆盖抽象方法并实现特定组骨架格式的子类。可以定义多种格式，并将对象实例变量设置为指示要使用的格式化程序。定义的接口和方法允许组格式化程序的可互换替换。

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