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1. 外观设计

USD676461S1 Governor 有权
公开(公告)号：USD676461S1
公开(公告)日：2013-02-19
申请号：US29406030
申请日：2011-11-09
申请人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa
设计人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa

2. 发明申请

US20090303812A1 PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路的可编程脉宽调制和延迟发生电路
公开(公告)号：US20090303812A1
公开(公告)日：2009-12-10
申请号：US12543256
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C7/00 , G11C8/10 , G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

3. 发明授权

US07304352B2 Alignment insensitive D-cache cell 有权
标题翻译：对齐不敏感的D缓存单元
公开(公告)号：US07304352B2
公开(公告)日：2007-12-04
申请号：US11111454
申请日：2005-04-21
申请人： K. Paul Muller , Kevin A. Batson , Michael J. Lee
发明人： K. Paul Muller , Kevin A. Batson , Michael J. Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.
摘要翻译：具有改进的示意图和布局设计的D缓存SRAM单元，其显示出来自电路原理图和物理单元布局视角的增加的对称性。也就是说，SRAM单元包括两个读取端口，并且通过在真实侧提供一个读取端口和在补充端上提供一个读取端口来最小化不对称性。通过从本地互连级别提供通向M1或金属化级别的通孔连接，通过从真实和补偿侧两者的交叉耦合上升到一个级别，不对称性在布局中另外最小化。此外，局部互连（MC）和栅极导体结构（PC）之间的距离已经在交叉锁存SRAM单元中的每个pFET被放大和均衡。因此，通过最大化这个MC-PC距离，SRAM单元已经对覆盖（局部互连处理太近）变得不敏感。

4. 发明授权

US06791855B2 Redundant array architecture for word replacement in CAM 有权
标题翻译： CAM中字替换的冗余阵列架构
公开(公告)号：US06791855B2
公开(公告)日：2004-09-14
申请号：US10641753
申请日：2003-08-14
申请人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C1500
CPC分类号： G11C29/816 , G11C15/00
摘要： The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
摘要翻译：本发明提供了一种存储器架构，其允许通过已经提供在芯片上的未增加芯片尺寸的备用元件进行存储器检查和替换缺陷字。本发明的方法使用单独的冗余阵列架构来提供地址转换，使得冗余条目被表示为正在替换的正确条目索引。

5. 发明授权

US06687144B2 High reliability content-addressable memory using shadow content-addressable memory 失效
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06687144B2
公开(公告)日：2004-02-03
申请号：US10430671
申请日：2003-05-06
申请人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容和可寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

6. 发明授权

US5646566A Low power clocked set/reset fast dynamic latch 失效
标题翻译：低功耗时钟设置/复位快速动态锁存
公开(公告)号：US5646566A
公开(公告)日：1997-07-08
申请号：US667682
申请日：1996-06-21
申请人： Robert A. Ross, Jr. , Kevin A. Batson
发明人： Robert A. Ross, Jr. , Kevin A. Batson
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/356156 , H03K3/012
摘要： A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.
摘要翻译：动态锁存电路设计可最大限度地降低设置和恢复功耗，而不会牺牲速度。与传统的动态锁存器设计相比，动态锁存电路提供了两个显着的省电优势。第一个调节动态恢复功率与锁存器的状态。如果锁存器的动态内部节点未放电，则施加到锁存器输入端的恢复信号不会传送到连接到该节点的恢复设备。通过在这些条件下隔离恢复设备，额外的电源不会浪费已经预充电节点的引导。第二，按设计，恢复路径和设置路径是分开的。用于设置锁存器的输入信号是不同的，与执行恢复的输入信号隔离。因此，当恢复装置打开时，电压源和电路地之间没有导通路径。

7. 发明授权

US06650561B2 High reliability content-addressable memory using shadow content-addressable memory 有权
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06650561B2
公开(公告)日：2003-11-18
申请号：US10059863
申请日：2002-01-30
申请人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

8. 发明授权

US06430073B1 Dram CAM cell with hidden refresh 有权
标题翻译：具有隐藏刷新功能的CAM CAM单元
公开(公告)号：US06430073B1
公开(公告)日：2002-08-06
申请号：US09730673
申请日：2000-12-06
申请人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch
发明人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.
摘要翻译：动态内容可寻址存储器（DCAM）单元拓扑，其包含较少的可以执行不会延迟或中断CAM搜索周期的存储数据的“隐藏”刷新，从而提供类似SCAM的性能。执行非破坏性读取操作，使得由于刷新读取操作而不必将所存储的数据写回。可以在读取操作之后，甚至在刷新数据被写回之前执行可靠的CAM搜索。可以在更新周期的未决期间对每个CAM条目执行软错误检测处理。 DCAM单元可用于数字系统，如数字计算机和网络路由器。

9. 发明授权

US06282144B1 Multi-ported memory with asynchronous and synchronous protocol 有权
标题翻译：具有异步和同步协议的多端口存储器
公开(公告)号：US06282144B1
公开(公告)日：2001-08-28
申请号：US09524661
申请日：2000-03-13
申请人： Kevin A. Batson , Garrett S. Koch , Sebastian T. Ventrone
发明人： Kevin A. Batson , Garrett S. Koch , Sebastian T. Ventrone
IPC分类号： G11C800
CPC分类号： G06F13/1684 , G11C8/16
摘要： A multi-port memory is provided that includes means for receiving synchronous memory requests, means for receiving asynchronous memory requests, and means for processing the received synchronous and asynchronous memory requests simultaneously. Systems and methods that employ the multi-port memory are also provided.
摘要翻译：提供了一种多端口存储器，其包括用于接收同步存储器请求的装置，用于接收异步存储器请求的装置，以及用于同时处理所接收的同步和异步存储器请求的装置。还提供了使用多端口存储器的系统和方法。

10. 发明授权

US5778428A Programmable high performance mode for multi-way associative cache/memory designs 失效
标题翻译：可编程高性能模式，用于多路关联高速缓存/内存设计
公开(公告)号：US5778428A
公开(公告)日：1998-07-07
申请号：US577167
申请日：1995-12-22
申请人： Kevin A. Batson , Robert A. Ross, Jr.
发明人： Kevin A. Batson , Robert A. Ross, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02B60/1225
摘要： The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.
摘要翻译：本发明提供了便于用户选择替代存储器存取技术的电路。本发明提供了一种设计方法或技术，用于将与等待有效的“路选”信号相关联的时间转换为周期缩短时间，从而提供多路关联高速缓存和存储器设计的整体性能的有益增加。

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