专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07678623B2 Staggered source/drain and thin-channel TFT structure and fabrication method thereof 失效
标题翻译：交错源极/漏极和薄沟道TFT结构及其制造方法
公开(公告)号：US07678623B2
公开(公告)日：2010-03-16
申请号：US11410168
申请日：2006-04-24
申请人： Kow-Ming Chang , Gin-Min Lin
发明人： Kow-Ming Chang , Gin-Min Lin
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/66757 , H01L29/78609 , H01L29/78618
摘要： This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.
摘要翻译：本发明涉及一种用于制造交错的源极/漏极和薄沟道TFT结构的方法，其通过减少掩模步骤的数量并且在抑制漏极结附近的电场方面获得更好的结果来简化制造结构的常规工艺，以及减少漏电流。该方法包括（1）将a-Si重结晶成多晶硅（O 2），其通过在衬底上沉积a-Si层然后施加一般的光刻步骤和RIE蚀刻步骤来定义非晶Si 设置有较高区域和较低区域的岛，其中a-Si的薄沟道的残留宽度在蚀刻后为约5至200nm; 然后在随后的退火之后将a-Si变成多晶硅（O 2）; （2）限定栅极区（05），源极/漏极区（07）和沟道; （3）应用植入; 和（4）应用连接。

2. 发明授权

US06284621B1 Semiconductor structure with a dielectric layer and its producing method 有权
标题翻译：具有介电层的半导体结构及其制造方法
公开(公告)号：US06284621B1
公开(公告)日：2001-09-04
申请号：US09239000
申请日：1999-01-27
申请人： Kow-Ming Chang , Ji-Yi Yang
发明人： Kow-Ming Chang , Ji-Yi Yang
IPC分类号： H01L21764
CPC分类号： H01L21/7682
摘要： A semiconductor structure with a dielectric layer and its producing method are disclosed. The semiconductor structure includes a semiconductor substrate having thereon a plurality of metal lines and there are a plurality of concave regions formed between the metal lines. The dielectric layer is formed on the semiconductor by a method which can prevent the dielectric material from flowing into the concave regions. The method includes the steps of (a) providing a semiconductor substrate having thereon a plurality of metal lines forming therebetween a plurality of concave regions; and (b) forming the dielectric layer on the metal lines. The concave regions are only filled with air so that the capacitance of the semiconductor is lowered.
摘要翻译：公开了具有介电层的半导体结构及其制造方法。半导体结构包括其上具有多个金属线的半导体衬底，并且在金属线之间形成有多个凹区。通过可以防止电介质材料流入凹入区域的方法在半导体上形成电介质层。该方法包括以下步骤：（a）提供其上形成有多个金属线之间的多个凹陷区域的半导体衬底; 和（b）在金属线上形成电介质层。凹区仅填充有空气，使得半导体的电容降低。

3. 发明授权

US06969890B2 Structure of thin film transistor 失效
标题翻译：薄膜晶体管的结构
公开(公告)号：US06969890B2
公开(公告)日：2005-11-29
申请号：US10632641
申请日：2003-08-01
申请人： Kow Ming Chang , Yuan Hung Chung
发明人： Kow Ming Chang , Yuan Hung Chung
IPC分类号： H01L21/336 , H01L29/786 , H01L29/72
CPC分类号： H01L29/66772 , H01L29/78645
摘要： A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.
摘要翻译：公开了一种制造用于解决现有技术缺点的薄膜晶体管的方法。该方法包括以下步骤：在绝缘基板上提供绝缘基板，顺序地形成源极/漏极层，主栅极绝缘层和第一导电层，蚀刻第一导电层以形成主栅极; 在主栅极上依次形成次级栅极绝缘层和第二导电层; 以及蚀刻所述第二导电层以形成第一辅助栅极和第二次栅极。

4. 发明授权

US06194295B1 Production of a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal 有权
$Production of a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal$
标题翻译：通过双层堆叠的钨金属的化学气相沉积生产难熔金属
公开(公告)号：US06194295B1
公开(公告)日：2001-02-27
申请号：US09312483
申请日：1999-05-17
申请人： Kow-Ming Chang , I-Chung Deng , Ta-Hsun Yeh
发明人： Kow-Ming Chang , I-Chung Deng , Ta-Hsun Yeh
IPC分类号： H01L213205
CPC分类号： H01L21/28568 , C23C16/14 , C23C16/56 , H01L21/28044 , H01L21/76843 , H01L21/76856
摘要： Provided a process for producing a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal by depositing a bilayer-stacked tungsten metal in a same chamber in the manner of not breaking the vacuum therein. Firstly, a layer of amorphous-like tungsten is deposited to increase thermal stability and to prevent diffusion of fluorine atom. Next, a nitridizing treatment is performed thereon to promote further the barrier property and thermal stability of the amorphous-like tungsten. Finally, conventional selective chemical vapor deposited tungsten having low is deposited on the amorphous-like tungsten. Through the deposition of bilayer tungsten according to the process of the invention, thermal stability of conventional selective chemical vapor deposited tungsten can be increased greatly. For the manufacture of a extremely large integrated circuit, stacked tungsten not only can prevent fluorine atom from diffusing downwardly in the course of deposition, but also can increase thermal stability, and furthermore, the resistance thereof is much lower that that of tungsten disilicide. Accordingly, the process of the invention is indeed a technique having high potential.
摘要翻译：提供一种通过双层堆叠的钨金属的化学气相沉积制造难熔金属的方法，方法是以不破坏真空的方式在相同的室中沉积双层堆叠的钨金属。首先，沉积一层非晶态钨以提高热稳定性并防止氟原子的扩散。接着，进行氮化处理，进一步促进非晶态钨的阻隔性和热稳定性。最后，传统的选择性化学气相沉积的钨沉积在非晶态钨上。通过根据本发明的方法沉积双层钨，可以大大提高常规选择性化学气相沉积钨的热稳定性。为了制造极大的集成电路，堆积的钨不仅可以防止氟原子在沉积过程中向下扩散，而且还可以增加热稳定性，此外，其电阻远低于二硅化钨的电阻。因此，本发明的方法确实是具有高潜力的技术。

5. 发明授权

US6165844A Method for forming a textured surface on a semiconductor substrate and a tunneling oxide layer on the textured surface 有权
标题翻译：在纹理表面上在半导体衬底上形成纹理表面和隧道氧化物层的方法
公开(公告)号：US6165844A
公开(公告)日：2000-12-26
申请号：US195910
申请日：1998-11-19
申请人： Kow-Ming Chang
发明人： Kow-Ming Chang
IPC分类号： H01L21/28 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/42364 , H01L21/28167 , H01L21/28211 , H01L21/28273 , Y10S438/964
摘要： A method is provided for fabricating a tunneling oxide layer over a semiconductor substrate with a textured surface. The method is suitable for a semiconductor substrate, such as a silicon substrate, having a polysilicon layer formed over the substrate. The method has several steps of performing a thermal oxidation process to over oxidize the polysilicon layer so as to form an interfacial oxide layer between the substrate and the polysilicon layer, which actually is oxidized as an oxide layer. Due to material property of polysilicon, a textured surface is naturally formed on a top of the substrate. After removing the oxide layer and the interfacial oxide layer, a tunneling oxide layer is formed over the substrate with the textured surface.
摘要翻译：提供了一种用于在具有纹理表面的半导体衬底上制造隧道氧化物层的方法。该方法适合于在衬底上形成多晶硅层的诸如硅衬底的半导体衬底。该方法具有进行热氧化处理以过度氧化多晶硅层的几个步骤，以在衬底和多晶硅层之间形成界面氧化层，实际上氧化为氧化物层。由于多晶硅的材料性质，纹理表面天然地形成在衬底的顶部上。在去除氧化物层和界面氧化物层之后，在衬底上形成具有纹理化表面的隧道氧化物层。

6. 发明授权

US6046475A Structure and method for manufacturing devices having inverse T-shaped well regions 失效
标题翻译：用于制造具有反T形阱区的器件的结构和方法
公开(公告)号：US6046475A
公开(公告)日：2000-04-04
申请号：US864988
申请日：1997-05-29
申请人： Kow-Ming Chang , Ji-yi Yang , Ming-Ray Mao
发明人： Kow-Ming Chang , Ji-yi Yang , Ming-Ray Mao
IPC分类号： H01L29/10 , H01L31/119
CPC分类号： H01L29/1079
摘要： A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.
摘要翻译：用于制造具有反T形阱区的器件的结构，其形成在衬底上，包括具有较高杂质浓度的第一掺杂区和第二掺杂区和具有较低杂质浓度的两个第三掺杂区。通过高能离子注入工艺在衬底上形成的第一掺杂区域保持在离衬底表面预定距离处。第二掺杂区域从衬底的表面向下延伸以连接到第一掺杂区域，使得形成两个第二掺杂区域。第二掺杂区域通过离子注入工艺通过掩模的开口形成。此外，在第二掺杂区域上方形成栅极，并且在衬底上形成源极和漏极区域。因此，具有逆T形阱区域的器件被完全制造。

7. 发明授权

US06991973B2 Manufacturing method of thin film transistor 失效
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US06991973B2
公开(公告)日：2006-01-31
申请号：US10913584
申请日：2004-08-05
申请人： Kow Ming Chang , Yuan Hung Chung
发明人： Kow Ming Chang , Yuan Hung Chung
IPC分类号： H01L21/84
CPC分类号： H01L29/78645 , H01L29/66772
摘要： A method of manufacturing a thin film transistor for solving the drawbacks of the prior arts is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.
摘要翻译：公开了一种用于解决现有技术的缺陷的薄膜晶体管的制造方法。该方法包括以下步骤：在绝缘基板上提供绝缘基板，顺序地形成源极/漏极层，主栅极绝缘层和第一导电层，蚀刻第一导电层以形成主栅极; 在主栅极上依次形成次级栅极绝缘层和第二导电层; 以及蚀刻所述第二导电层以形成第一辅助栅极和第二次栅极。

8. 发明授权

US06281074B1 Method of manufacturing oxide layer 有权
标题翻译：氧化层的制造方法
公开(公告)号：US06281074B1
公开(公告)日：2001-08-28
申请号：US09224686
申请日：1999-01-04
申请人： Kow-Ming Chang
发明人： Kow-Ming Chang
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L21/32105
摘要： A method is described for manufacturing an oxide layer. A substrate is provided. An amorphous silicon layer is formed on the substrate. The amorphous silicon layer is recrystallized to form a polysilicon layer. The polysilicon layer is oxidized to form an oxide layer.
摘要翻译：描述了制造氧化物层的方法。提供基板。在基板上形成非晶硅层。将非晶硅层重结晶以形成多晶硅层。多晶硅层被氧化以形成氧化物层。

9. 发明授权

US5955200A Structure for reducing stress between metallic layer and spin-on-glass layer 失效
标题翻译：用于减少金属层和旋涂玻璃层之间的应力的结构
公开(公告)号：US5955200A
公开(公告)日：1999-09-21
申请号：US20946
申请日：1998-02-09
申请人： Kow-Ming Chang , Shih-Wei Wang
发明人： Kow-Ming Chang , Shih-Wei Wang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , B32B17/00
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/3124 , H01L21/31612 , H01L21/76819 , H01L21/76828 , H01L21/76834
摘要： A structure for reducing the stress between a HSQ dielectric layer and a metal layer. The structure comprises a metal layer, a stress buffer above the metal layer, and a spin-on-glass layer above the stress buffer. If the spin-on-glass layer is a dielectric material capable of producing tensile stress, the stress buffer layer is made from a material capable of generating compressive stress. On the contrary, if the spin-on-glass layer is a dielectric material capable of producing compressive stress, the stress buffer layer is made from a material capable of generating tensile stress.
摘要翻译：用于减小HSQ介电层和金属层之间的应力的结构。该结构包括金属层，金属层上方的应力缓冲层和应力缓冲器上方的旋涂玻璃层。如果旋涂玻璃层是能够产生拉伸应力的介电材料，则应力缓冲层由能够产生压应力的材料制成。相反，如果旋涂玻璃层是能够产生压应力的电介质材料，则应力缓冲层由能够产生拉伸应力的材料制成。

10. 发明申请

US20070161161A1 Staggered source/drain and thin-channel TFT structure and fabrication method thereof 失效
标题翻译：交错源极/漏极和薄沟道TFT结构及其制造方法
公开(公告)号：US20070161161A1
公开(公告)日：2007-07-12
申请号：US11410168
申请日：2006-04-24
申请人： Kow-Ming Chang , Gin-Min Lin
发明人： Kow-Ming Chang , Gin-Min Lin
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/66757 , H01L29/78609 , H01L29/78618
摘要： This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.
摘要翻译：本发明涉及一种用于制造交错的源极/漏极和薄沟道TFT结构的方法，其通过减少掩模步骤的数量并且在抑制漏极结附近的电场方面获得更好的结果来简化制造结构的常规工艺，以及减少漏电流。该方法包括（1）将a-Si重结晶成多晶硅（O 2），其通过在衬底上沉积a-Si层然后施加一般的光刻步骤和RIE蚀刻步骤来定义非晶Si 设置有较高区域和较低区域的岛，其中a-Si的薄沟道的残留宽度在蚀刻后为约5至200nm; 然后在随后的退火之后将a-Si变成多晶硅（O 2）; （2）限定栅极区（05），源极/漏极区（07）和沟道; （3）应用植入; 和（4）应用连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式