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1. 发明申请

US20120268207A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20120268207A1
公开(公告)日：2012-10-25
申请号：US13333766
申请日：2011-12-21
申请人： Kwan-Dong KIM
发明人： Kwan-Dong KIM
IPC分类号： H03F3/45
CPC分类号： H04L25/0276
摘要： An integrated circuit includes an input unit and a voltage level detecting unit. The input unit is configured to output differential amplification signals corresponding to differential input signals in response to a voltage level detection signal. The voltage level detecting unit is configured to detect a voltage level of the differential amplification signals and output the voltage level detection signal.
摘要翻译：集成电路包括输入单元和电压电平检测单元。输入单元被配置为响应于电压电平检测信号输出与差分输入信号相对应的差分放大信号。电压电平检测单元被配置为检测差分放大信号的电压电平并输出电压电平检测信号。

2. 发明授权

US08295121B2 Clock buffer and a semiconductor memory apparatus using the same 有权
标题翻译：时钟缓冲器和使用其的半导体存储装置
公开(公告)号：US08295121B2
公开(公告)日：2012-10-23
申请号：US12476387
申请日：2009-06-02
申请人： Kwan Dong Kim
发明人： Kwan Dong Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , G11C7/225
摘要： A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.
摘要翻译：时钟缓冲器包括参考使能信号发生器，其被配置为在启用时钟使能信号之后产生与第二时钟的第一周期的上升沿同步启用的参考使能信号，延迟使能信号发生器被配置为产生延迟使能在参考使能信号被使能之后与第一时钟的第二周期的上升沿同步地启用信号;第一输出单元，被配置为接收参考使能信号和第一时钟以产生第一内部时钟，第二输出单元，被配置为接收延迟的使能信号和第二时钟以产生第二内部时钟。

3. 发明授权

US08195107B2 Signal transmission system and signal transmission method thereof 有权
标题翻译：信号传输系统及其信号传输方法
公开(公告)号：US08195107B2
公开(公告)日：2012-06-05
申请号：US12346977
申请日：2008-12-31
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H01Q11/12
CPC分类号： H04B1/0475
摘要： A signal transmission system includes a transmitting unit configured to drive an input signal and to transmit the input signal, a pre-emphasis unit configured to detect a change in a voltage level of the input signal and to amplify a voltage of an output signal of the transmitting unit for a predetermined time, and a receiving unit configured to receive the output signal from the transmitting unit.
摘要翻译：信号传输系统包括被配置为驱动输入信号并传输输入信号的发送单元，配置为检测输入信号的电压电平的变化并且放大输入信号的输出信号的电压的预加重单元发送单元预定时间，以及接收单元，被配置为从发送单元接收输出信号。

4. 发明授权

US07880524B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07880524B2
公开(公告)日：2011-02-01
申请号：US12345735
申请日：2008-12-30
申请人： Kwan Dong Kim
发明人： Kwan Dong Kim
IPC分类号： H03H11/26
CPC分类号： H03L7/0812 , H03L7/10
摘要： A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.
摘要翻译： DLL电路包括：延迟单元，被配置为通过延迟参考时钟信号来产生DLL时钟信号，同时响应于控制电压的电平调整延迟量。初始操作控制单元被配置为控制控制电压的初始电平并产生检测使能信号。延迟控制单元被配置为响应于检测使能信号，通过比较参考时钟信号的相位和DLL时钟信号的相位来产生控制电压。

5. 发明授权

US07804727B2 Semiconductor device having multiple I/O modes 有权
标题翻译：具有多个I / O模式的半导体器件
公开(公告)号：US07804727B2
公开(公告)日：2010-09-28
申请号：US12164155
申请日：2008-06-30
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.
摘要翻译：具有多个I / O模式的半导体器件。该设备包括被配置为接收数据的数据缓冲器; 配置为接收数据选通信号的选通输入缓冲器;相位控制器，被配置为根据输入模式将数据选通信号的相位移位不同的度数，包括0度;以及数据检测器，被配置为检测响应中的数据到从相位控制器输出的数据选通信号。

6. 发明申请

US20100091592A1 CLOCK BUFFER AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME 有权
标题翻译：时钟缓冲器和使用其的半导体存储器设备
公开(公告)号：US20100091592A1
公开(公告)日：2010-04-15
申请号：US12476387
申请日：2009-06-02
申请人： Kwan Dong Kim
发明人： Kwan Dong Kim
IPC分类号： G11C7/00 , G11C8/18 , H03L7/00
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , G11C7/225
摘要： A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.
摘要翻译：时钟缓冲器包括参考使能信号发生器，其被配置为在启用时钟使能信号之后产生与第二时钟的第一周期的上升沿同步启用的参考使能信号，延迟使能信号发生器被配置为产生延迟使能在参考使能信号被使能之后与第一时钟的第二周期的上升沿同步地启用信号;第一输出单元，被配置为接收参考使能信号和第一时钟以产生第一内部时钟，第二输出单元，被配置为接收延迟的使能信号和第二时钟以产生第二内部时钟。

7. 发明申请

US20120153999A1 CLOCK SIGNAL GENERATION CIRCUIT 失效
标题翻译：时钟信号发生电路
公开(公告)号：US20120153999A1
公开(公告)日：2012-06-21
申请号：US13017270
申请日：2011-01-31
申请人： Kwan-Dong KIM
发明人： Kwan-Dong KIM
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/087 , H03L7/0895 , H03L7/093 , H03L7/10
摘要： A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal.
摘要翻译：时钟信号发生电路包括时钟反转单元，反相基准时钟信号和内部时钟信号以产生反相基准时钟信号和反相内部时钟信号;第一时钟检测单元，将参考时钟信号与内部时钟信号进行比较，输出第一检测信号，第二时钟检测单元，将反转的参考时钟信号与反相的内部时钟信号进行比较，以输出第二检测信号;响应于第一第二检测信号产生充电电流或放电电流的第一和第二电荷泵单元分别产生具有与充电电流或放电电流对应的电压电平的控制电压信号的环路滤波器单元，以及根据控制电压信号产生内部时钟信号的内部时钟信号输出单元。

8. 发明授权

US08138793B1 Integrated circuit and method for operating the same 失效
标题翻译：集成电路及其操作方法
公开(公告)号：US08138793B1
公开(公告)日：2012-03-20
申请号：US12981325
申请日：2010-12-29
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03K19/0175 , H03K19/20
CPC分类号： H03K19/0941 , H03K19/018528
摘要： An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.
摘要翻译：集成电路包括CML摆幅参考电压产生单元，CML偏置控制电压产生单元和CML缓冲单元。 CML摆幅参考电压产生单元响应于频率设置码和CML偏置控制电压来确定CML摆幅参考电压的电平。 CML偏置控制电压发生单元将CML摆幅参考电压的电平与CML目标参考电压的电平进行比较，并根据比较结果确定CML偏置控制电压的电平。 CML缓冲单元通过缓冲输入信号产生在CML区域中摆动的CML输出信号，并根据频率设定码和CML摆动参考电压的电平，根据CML摆动参考电压的电平确定CML输出信号的摆幅电平 CML偏置控制电压。

9. 发明申请

US20110291722A1 PHASE CORRECTION CIRCUIT 有权
标题翻译：相位校正电路
公开(公告)号：US20110291722A1
公开(公告)日：2011-12-01
申请号：US12981468
申请日：2010-12-29
申请人： Kwan Dong KIM
发明人： Kwan Dong KIM
IPC分类号： H03L7/00
CPC分类号： H03K5/15013 , G11C7/222 , G11C11/4076 , H03K5/135 , H03K2005/00052
摘要： A phase correction circuit includes a skew detection unit configured to generate first skew detection signals and second skew detection signals by comparing multi-phase signals with one another, a phase control signal generation unit configured to generate a plurality of phase control signals by combining the first skew detection signals with the second skew detection signals, and a phase adjustment unit configured to delay the multi-phase signals by delay time corresponding to the plurality of the phase control signals.
摘要翻译：相位校正电路包括：偏斜检测单元，被配置为通过将多相信号彼此进行比较来产生第一偏斜检测信号和第二偏斜检测信号;相位控制信号生成单元，被配置为通过将第一具有第二偏移检测信号的偏斜检测信号，以及相位调整单元，被配置为通过与多个相位控制信号相对应的延迟时间来延迟多相信号。

10. 发明授权

US08004314B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08004314B2
公开(公告)日：2011-08-23
申请号：US12616464
申请日：2009-11-11
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03K19/094
CPC分类号： H03K19/0005 , H03K19/01721 , H04L25/0278
摘要： A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line.
摘要翻译：半导体器件能够终止内部传输线并且包括被配置为产生对应于输出数据信号的上拉驱动信号和下拉驱动信号的预驱动单元，并且传送上拉驱动信号和分别驱动信号到第一传输线和第二传输线;主驱动单元，被配置为响应于上拉驱动信号和通过第一传输线传输的下拉驱动信号来驱动输出数据以及第二传输线和终端单元，被配置为提供终端电压以终止第一传输线和第二传输线。

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