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1. 发明授权

US08195107B2 Signal transmission system and signal transmission method thereof 有权
标题翻译：信号传输系统及其信号传输方法
公开(公告)号：US08195107B2
公开(公告)日：2012-06-05
申请号：US12346977
申请日：2008-12-31
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H01Q11/12
CPC分类号： H04B1/0475
摘要： A signal transmission system includes a transmitting unit configured to drive an input signal and to transmit the input signal, a pre-emphasis unit configured to detect a change in a voltage level of the input signal and to amplify a voltage of an output signal of the transmitting unit for a predetermined time, and a receiving unit configured to receive the output signal from the transmitting unit.
摘要翻译：信号传输系统包括被配置为驱动输入信号并传输输入信号的发送单元，配置为检测输入信号的电压电平的变化并且放大输入信号的输出信号的电压的预加重单元发送单元预定时间，以及接收单元，被配置为从发送单元接收输出信号。

2. 发明授权

US07804727B2 Semiconductor device having multiple I/O modes 有权
标题翻译：具有多个I / O模式的半导体器件
公开(公告)号：US07804727B2
公开(公告)日：2010-09-28
申请号：US12164155
申请日：2008-06-30
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.
摘要翻译：具有多个I / O模式的半导体器件。该设备包括被配置为接收数据的数据缓冲器; 配置为接收数据选通信号的选通输入缓冲器;相位控制器，被配置为根据输入模式将数据选通信号的相位移位不同的度数，包括0度;以及数据检测器，被配置为检测响应中的数据到从相位控制器输出的数据选通信号。

3. 发明授权

US08138793B1 Integrated circuit and method for operating the same 失效
标题翻译：集成电路及其操作方法
公开(公告)号：US08138793B1
公开(公告)日：2012-03-20
申请号：US12981325
申请日：2010-12-29
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03K19/0175 , H03K19/20
CPC分类号： H03K19/0941 , H03K19/018528
摘要： An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.
摘要翻译：集成电路包括CML摆幅参考电压产生单元，CML偏置控制电压产生单元和CML缓冲单元。 CML摆幅参考电压产生单元响应于频率设置码和CML偏置控制电压来确定CML摆幅参考电压的电平。 CML偏置控制电压发生单元将CML摆幅参考电压的电平与CML目标参考电压的电平进行比较，并根据比较结果确定CML偏置控制电压的电平。 CML缓冲单元通过缓冲输入信号产生在CML区域中摆动的CML输出信号，并根据频率设定码和CML摆动参考电压的电平，根据CML摆动参考电压的电平确定CML输出信号的摆幅电平 CML偏置控制电压。

4. 发明授权

US08004314B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08004314B2
公开(公告)日：2011-08-23
申请号：US12616464
申请日：2009-11-11
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03K19/094
CPC分类号： H03K19/0005 , H03K19/01721 , H04L25/0278
摘要： A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line.
摘要翻译：半导体器件能够终止内部传输线并且包括被配置为产生对应于输出数据信号的上拉驱动信号和下拉驱动信号的预驱动单元，并且传送上拉驱动信号和分别驱动信号到第一传输线和第二传输线;主驱动单元，被配置为响应于上拉驱动信号和通过第一传输线传输的下拉驱动信号来驱动输出数据以及第二传输线和终端单元，被配置为提供终端电压以终止第一传输线和第二传输线。

5. 发明授权

US08653866B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US08653866B2
公开(公告)日：2014-02-18
申请号：US12630252
申请日：2009-12-03
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/101 , H03L7/0816
摘要： A semiconductor device includes a control voltage generating block configured to generate a control voltage corresponding to a phase difference between a reference clock signal and an internal clock signal, a control voltage restoring block configured to store the control voltage as a restoring voltage when entering into a low power mode and to supply the restoring voltage to a control voltage node when exiting from the low power mode, and an internal clock signal generating block configured to generate the internal clock signal corresponding to a voltage level of the control voltage.
摘要翻译：一种半导体器件包括：控制电压产生块，被配置为产生与参考时钟信号和内部时钟信号之间的相位差相对应的控制电压;控制电压恢复块，被配置为在进入时钟信号时存储控制电压作为恢复电压低功率模式，并且当从低功率模式退出时将恢复电压提供给控制电压节点;以及内部时钟信号生成模块，被配置为产生对应于控制电压的电压电平的内部时钟信号。

6. 发明申请

US20130163367A1 CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE EMPLOYING THE SAME 有权
标题翻译：时钟发生电路和使用其的半导体存储器件
公开(公告)号：US20130163367A1
公开(公告)日：2013-06-27
申请号：US13606203
申请日：2012-09-07
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03H11/26 , G11C8/18
CPC分类号： G11C7/1066 , G11C7/222
摘要： A semiconductor memory device includes a first internal clock generation circuit configured to generate a first internal clock by compensating an external clock signal for a transfer delay thereof in the semiconductor memory device, a control voltage generation circuit configured to generate a control voltage in response to a profile selection signal, a second internal clock generation circuit configured to generate a second internal clock signal by delaying the first internal clock signal by a time corresponding to the control voltage, a selection output circuit configured to select one of the first internal clock signal and the second internal clock signal in response to a path selection signal and output a selected signal as a synchronization clock signal, and a data output circuit configured to output a data in synchronization with the synchronization clock signal.
摘要翻译：半导体存储器件包括：第一内部时钟产生电路，被配置为通过补偿半导体存储器件中的传输延迟的外部时钟信号来产生第一内部时钟;控制电压生成电路，被配置为响应于配置为通过将第一内部时钟信号延迟与控制电压对应的时间来产生第二内部时钟信号的第二内部时钟生成电路;选择输出电路，被配置为选择第一内部时钟信号和响应于路径选择信号输出第二内部时钟信号，并输出所选择的信号作为同步时钟信号;以及数据输出电路，被配置为与所述同步时钟信号同步地输出数据。

7. 发明授权

US08358160B2 Clock signal generation circuit 失效
标题翻译：时钟信号发生电路
公开(公告)号：US08358160B2
公开(公告)日：2013-01-22
申请号：US13017270
申请日：2011-01-31
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/087 , H03L7/0895 , H03L7/093 , H03L7/10
摘要： A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal.
摘要翻译：时钟信号发生电路包括时钟反转单元，反相基准时钟信号和内部时钟信号以产生反相基准时钟信号和反相内部时钟信号;第一时钟检测单元，将参考时钟信号与内部时钟信号进行比较，输出第一检测信号，第二时钟检测单元，将反转的参考时钟信号与反相的内部时钟信号进行比较，以输出第二检测信号;响应于第一第二检测信号产生充电电流或放电电流的第一和第二电荷泵单元分别产生具有与充电电流或放电电流对应的电压电平的控制电压信号的环路滤波器单元，以及根据控制电压信号产生内部时钟信号的内部时钟信号输出单元。

8. 发明申请

US20110156779A1 PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME 有权
标题翻译：相位锁定环及其操作方法
公开(公告)号：US20110156779A1
公开(公告)日：2011-06-30
申请号：US12648816
申请日：2009-12-29
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03L7/08
CPC分类号： H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/0995
摘要： A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.
摘要翻译：锁相环包括相位锁定单元，被配置为将参考时钟的相位与反馈时钟的相位进行比较，并且基于该比较来产生内部时钟; 延迟锁定单元，被配置为将所述参考时钟与所述内部时钟进行比较，并且产生响应于基于所述比较的控制电压被延迟的所述反馈时钟; 以及启动电压启动单元，被配置为响应于使能信号接收使能信号并施加起始电压作为控制电压。

9. 发明申请

US20110001510A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110001510A1
公开(公告)日：2011-01-06
申请号：US12616464
申请日：2009-11-11
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/01721 , H04L25/0278
摘要： A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line.
摘要翻译：半导体器件能够终止内部传输线并且包括被配置为产生对应于输出数据信号的上拉驱动信号和下拉驱动信号的预驱动单元，并且传送上拉驱动信号和分别驱动信号到第一传输线和第二传输线;主驱动单元，被配置为响应于上拉驱动信号和通过第一传输线传输的下拉驱动信号来驱动输出数据以及第二传输线和终端单元，被配置为提供终端电压以终止第一传输线和第二传输线。

10. 发明申请

US20080284527A1 PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME 有权
标题翻译：相位锁定环及其操作方法
公开(公告)号：US20080284527A1
公开(公告)日：2008-11-20
申请号：US11967839
申请日：2007-12-31
申请人： Kwan-Dong Kim
发明人： Kwan-Dong Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/18
摘要： A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator.
摘要翻译：锁相环可以减少锁定时间，从而在锁定操作中有效降低功率。锁相环包括相位检测器，控制电压发生器，压控振荡器和启动驱动器。相位检测器检测参考时钟和反馈时钟之间的相位差，以产生对应于检测到的相位差的检测信号。控制电压发生器产生具有与检测信号对应的电压电平的控制电压。压控振荡器产生具有对应于控制电压的电压电平的频率的内部时钟。启动驱动器响应于在激活压控振荡器之前对应于参考时钟的频率的启动电平复用信号，将控制电压端驱动到预定的起动电平。

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