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1. 发明授权

US09298106B1 Wafer stage with reciprocating wafer stage actuation control 有权
标题翻译：晶圆台采用往复式晶片台致动控制
公开(公告)号：US09298106B1
公开(公告)日：2016-03-29
申请号：US13606951
申请日：2012-09-07
申请人： Upendra Ummethala , Marek Zywno , Layton Hale
发明人： Upendra Ummethala , Marek Zywno , Layton Hale
IPC分类号： G03F7/20 , H01L21/68
CPC分类号： G03F7/70758 , G03F7/70725 , G03F7/70775 , H01L21/68
摘要： A wafer stage system with reciprocating wafer stage actuation control may include a wafer stage, a motor configured to actuate the wafer stage in a first and/or second direction along an axis, a first reciprocating mechanism configured to decelerate the wafer stage after the wafer stage is actuated to a desired position in the first direction, the first reciprocating mechanism configured to store energy captured while decelerating the wafer stage in the first direction, the first reciprocating mechanism configured to accelerate the wafer stage in the second direction, and a second reciprocating mechanism configured to decelerate the wafer stage after the wafer stage is actuated to a desired position in the second direction, the second reciprocating mechanism configured to store energy captured while decelerating the wafer stage in the second direction, the second reciprocating mechanism further configured to accelerate the wafer stage in the first direction.
摘要翻译：具有往复式晶片台致动控制的晶片台系统可以包括晶片台，被配置为沿着轴线沿第一和/或第二方向致动晶片台的电动机，第一往复运动机构，其被配置为在晶片台之后减速晶片台所述第一往复运动机构被配置为在第一方向减速晶片台时存储捕获的能量，所述第一往复运动机构构造成在第二方向上加速所述晶片台;以及第二往复运动机构被配置为在所述晶片台被致动到所述第二方向上的期望位置之后使所述晶片台减速，所述第二往复运动机构构造成存储在第二方向减速所述晶片台时所捕获的能量，所述第二往复运动机构进一步构造成加速所述晶片在第一个方向的阶段。

2. 发明申请

US20130293865A1 Linear Stage for Reflective Electron Beam Lithography 有权
标题翻译：反射电子束光刻线性阶段
公开(公告)号：US20130293865A1
公开(公告)日：2013-11-07
申请号：US13824079
申请日：2012-09-06
申请人： Upendra Ummethala , Layton Hale , Joshua Clyne , Samir Nayfeh , Mark Williams , Joseph A. Di Regolo , Andrew Wilson
发明人： Upendra Ummethala , Layton Hale , Joshua Clyne , Samir Nayfeh , Mark Williams , Joseph A. Di Regolo , Andrew Wilson
IPC分类号： G03F7/20
CPC分类号： G03F7/70716 , B82Y10/00 , B82Y40/00 , G03F7/70758 , G03F7/70766 , H01J37/20 , H01J37/3174 , H01J2237/20221 , H01J2237/31774 , H01J2237/31789
摘要： A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.
摘要翻译：适用于REBL的线性堆叠级可以包括第一上部快速级，其被配置为沿着第一轴沿第一方向平移第一多个晶片，所述第一上部快速级被配置为固定第一多个晶片; 第二上快速级，被配置为沿第一轴在第二方向上平移第二多个晶片，第二上快速级被配置为固定第二多个晶片，第二方向与第一方向相反，其中，第一上快速阶段和第二上快速阶段的平移被配置为基本上消除由第一上快速阶段和第二上快速阶段的运动产生的惯性反作用力; 以及载体台，其构造成沿着第二轴平移所述第一和第二上部快速级。

3. 发明授权

US09690213B2 Linear Stage for reflective electron beam lithography 有权
公开(公告)号：US09690213B2
公开(公告)日：2017-06-27
申请号：US13824079
申请日：2012-09-06
申请人： Upendra Ummethala , Layton Hale , Joshua Clyne , Samir Nayfeh , Mark Williams , Joseph A. Di Regolo , Andrew Wilson
发明人： Upendra Ummethala , Layton Hale , Joshua Clyne , Samir Nayfeh , Mark Williams , Joseph A. Di Regolo , Andrew Wilson
IPC分类号： G03F7/20 , H01J37/20 , H01J37/317 , B82Y10/00 , B82Y40/00
CPC分类号： G03F7/70716 , B82Y10/00 , B82Y40/00 , G03F7/70758 , G03F7/70766 , H01J37/20 , H01J37/3174 , H01J2237/20221 , H01J2237/31774 , H01J2237/31789
摘要： A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.

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