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1. 发明授权

US09242858B2 Instruction register delay select outputs to clock delay circuitry 有权
标题翻译：指令寄存器延迟选择输出到时钟延迟电路
公开(公告)号：US09242858B2
公开(公告)日：2016-01-26
申请号：US13097362
申请日：2011-04-29
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G06F11/00 , B82Y25/00 , G01R31/3185 , G01R33/09
CPC分类号： G01R31/31717 , B82Y25/00 , G01R31/31701 , G01R31/31723 , G01R31/31727 , G01R31/3177 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318572 , G01R33/093
摘要： A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.
摘要翻译：传播测试指令，衰减测试指令和循环测试指令提供包括JTAG边界扫描单元在内的电路之间的直流和交流互连电路的测试。测试访问端口电路的一些补充，包括门控产生捕捉测试频闪（CTS）信号和边界扫描单元需要实施附加说明。说明书是常规JTAG操作结构的扩展。

2. 发明授权

US08941109B2 Test output buffer functional output input, test output, enable input 有权
标题翻译：测试输出缓冲区功能输出输入，测试输出，使能输入
公开(公告)号：US08941109B2
公开(公告)日：2015-01-27
申请号：US14258651
申请日：2014-04-22
申请人： Lee D. Whetsel , Richard L. Antley
发明人： Lee D. Whetsel , Richard L. Antley
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： G01R31/2886 , G01R1/0491 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
摘要翻译：晶片上的晶片的及时测试降低了制造IC的成本。本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。添加的测试垫允许测试仪同时探测和测试模具中的更多电路。此外，添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量，从而减小管芯尺寸。

3. 发明授权

US08910003B2 Controller circuitry with state machines, address store/compare, and shift register 有权
标题翻译：具有状态机的控制器电路，地址存储/比较和移位寄存器
公开(公告)号：US08910003B2
公开(公告)日：2014-12-09
申请号：US14297051
申请日：2014-06-05
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/31723 , G01R31/31722 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318572 , G06F11/261 , G06F11/267 , G06F11/27 , G06F11/3466
摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
摘要翻译：地址和命令端口接口选择性地启用IC内的JTAG TAP域操作和跟踪域操作。端口在单个引脚上承载TMS和TDI输入和TDO输出，并在单独的引脚上接收时钟信号。可寻址的两个引脚接口将指令和数据加载并更新到IC内的TAP域。多个IC中的指令或数据更新操作同时发生。过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。标头位的逻辑电平用于启动，继续和停止向控制器传输数据。控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。

4. 发明授权

US08604475B2 IC dies with serarate connections to expected and mask data 有权
标题翻译： IC死亡与预期和掩模数据的serarate连接
公开(公告)号：US08604475B2
公开(公告)日：2013-12-10
申请号：US13629854
申请日：2012-09-28
申请人： Lee D. Whetsel , Alan Hales
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

5. 发明授权

US08560905B2 Programmable test compression architecture with serial input register and multiplexer 有权
标题翻译：具有串行输入寄存器和多路复用器的可编程测试压缩架构
公开(公告)号：US08560905B2
公开(公告)日：2013-10-15
申请号：US13343998
申请日：2012-01-05
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/3172 , G01R31/31723 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G06F11/2733
摘要： The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了使用并行或串行访问技术在设备中访问测试压缩架构（TCA）的新颖的方法和装置。串行访问技术可以由设备测试者或JTAG控制器控制。此外，本公开提供了当设备以与其他设备（例如客户系统）中的菊花链布置存在时访问设备的TCA的方法。在本公开中还提供和描述了另外的实施例。

6. 发明授权

US08412995B2 TAP and AUX with IR control of TDI input multiplexer 有权
标题翻译： TAP和AUX与TDI输入多路复用器的IR控制
公开(公告)号：US08412995B2
公开(公告)日：2013-04-02
申请号：US13439454
申请日：2012-04-04
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/2851 , G01R31/3177 , G01R31/318536 , G01R31/318572 , G01R31/318594
摘要： The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
摘要翻译：本公开描述了用于直接访问存在于许多串行连接的JTAG Tap域的扫描路径中的JTAG Tap域的新颖的方法和装置。由JTAG控制器直接扫描访问所选的Tap域，可以使用与Tap域关联并连接到JTAG控制器的辅助数字或模拟终端。在直接扫描访问期间，辅助数字或模拟端子用作所选Tap域和JTAG控制器之间的串行数据输入和串行数据输出路径。

7. 发明授权

US08402331B2 Signal connections extending from the periphery of an IP core 有权
标题翻译：信号连接从IP核的外围延伸
公开(公告)号：US08402331B2
公开(公告)日：2013-03-19
申请号：US13486138
申请日：2012-06-01
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318541 , G01R31/318555 , G01R31/318586
摘要： An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
摘要翻译：集成电路具有知识产权核心。知识产权核心包括测试访问端口39，测试数据输入引线15，测试数据输出引线13，控制引线17和存在的外部寄存器ERP导线37.扫描寄存器25包含知识产权核心和ERP引导线37携带指示存在扫描寄存器的信号。

8. 发明授权

US08402330B2 Selecting on die test port and off die interface leads 有权
标题翻译：选择裸片测试端口和离线接口引线
公开(公告)号：US08402330B2
公开(公告)日：2013-03-19
申请号：US13370521
申请日：2012-02-10
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318505 , G01R31/318555 , G06F11/267
摘要： An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.
摘要翻译： IC包括IEEE 1149.1标准测试接入端口（TAP）接口和附加的片外TAP接口。片外TAP接口连接到另一个IC的TAP。芯片TAP接口可以通过IC上的TAP链接模块来选择。

9. 发明授权

US08392774B2 Receiving control signals and operating separate scan paths with adaptor 有权
标题翻译：接收控制信号并用适配器操作单独的扫描路径
公开(公告)号：US08392774B2
公开(公告)日：2013-03-05
申请号：US13167418
申请日：2011-06-23
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G01R31/318575 , G01R31/318577
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本公开描述了将常规扫描架构适应成低功耗扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更少的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

10. 发明授权

US08386865B2 Taps with link update, data, instruction, and augmentation registers 有权
标题翻译：带有链接更新，数据，指令和增强寄存器的抽头
公开(公告)号：US08386865B2
公开(公告)日：2013-02-26
申请号：US13559251
申请日：2012-07-26
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

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