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    • 2. 发明授权
    • Display device and repairing method therefor
    • 显示装置及其修理方法
    • US08284377B2
    • 2012-10-09
    • US12553973
    • 2009-09-03
    • Je-Hao HsuWen-Pin ChenChiu-Mei YuLee-Hsun Chang
    • Je-Hao HsuWen-Pin ChenChiu-Mei YuLee-Hsun Chang
    • G02F1/1333G02F1/13G02F1/1345G06F3/038G09G3/36
    • G02F1/136259G09G3/3677G09G2330/08
    • In a display device and a repairing method therefor, the display device includes a gate line and two gate-on-array circuits arranged at two sides thereof. Each of the gate-on-array circuits includes a stage coupled to the gate line. Each the stage includes a transistor and a repair circuit. The first source/drain electrode of the transistor is coupled to the gate line, and the second source/drain electrode of the transistor is coupled to receive a clock pulse signal. The repair circuit includes a first terminal coupled to the gate electrode of the transistor, a second terminal coupled to a predetermined potential, and at least one control terminal adapted to receive at least one repair signal to pull the potential on the gate electrode of the transistor to the predetermined potential. The transistor maintains at off-state when the at least one repair signal is supplied to the repair circuit.
    • 在显示装置及其修复方法中,显示装置包括设置在其两侧的栅极线和两个栅极阵列电路。 栅阵列电路中的每一个包括耦合到栅极线的级。 每个级包括晶体管和修复电路。 晶体管的第一源/漏电极耦合到栅极线,并且晶体管的第二源极/漏极电极被耦合以接收时钟脉冲信号。 修复电路包括耦合到晶体管的栅电极的第一端子,耦合到预定电位的第二端子,以及至少一个控制端子,适于接收至少一个修复信号以拉动晶体管的栅电极上的电位 达到预定的电位。 当至少一个修复信号被提供给修复电路时,晶体管保持断开状态。
    • 4. 发明申请
    • SHIFT REGISTER
    • 移位寄存器
    • US20100054392A1
    • 2010-03-04
    • US12429018
    • 2009-04-23
    • Wen-pin ChenLee-hsun ChangJe-hao Hsu
    • Wen-pin ChenLee-hsun ChangJe-hao Hsu
    • G11C19/00
    • G11C19/28G09G2310/0286G09G2320/0266
    • A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.
    • 移位寄存器包括彼此串联连接的多个级。 每个级包括上拉电路,上拉驱动电路和下拉电路。 耦合到第一时钟信号的上拉电路用于提供输出信号。 上拉驱动电路包括控制电路和第一晶体管。 控制电路具有耦合到前一级的栅极和耦合到第二时钟信号的漏极。 第一晶体管包括耦合到控制电路的源极的栅极,耦合到前一级的驱动端的漏极和耦合到第一输入端的源极。 下拉电路拉低第一个输入端的电压。
    • 5. 发明申请
    • GATE DRIVER-ON-ARRAY STRUCTURE AND DISPLAY PANEL
    • 门控驱动器 - 阵列结构和显示面板
    • US20090166632A1
    • 2009-07-02
    • US12147488
    • 2008-06-27
    • Lee-Hsun Chang
    • Lee-Hsun Chang
    • H01L27/12
    • H01L27/124
    • A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of the bar-like conductive layer. The first conductive patterns and the second conductive patterns are disposed on the semiconductor layer and located within the regions. The bar-like conductive layer is located between the first electrode line and the second electrode line. The first electrode line and the second electrode line are respectively spaced from the bar-like conductive layer by a first distance and a second distance. The GOA structure has first connectors connected to the corresponding first conductive patterns and the first electrode line, and second connectors connected to the second conductive patterns and the second electrode line.
    • 集成在显示面板中的栅极驱动器阵列结构包括棒状导电层,半导体层,第一导电图案,第二导电图案,第一电极线和第二电极线。 棒状导电层具有多个区域。 半导体层设置在棒状导电层的区域内。 第一导电图案和第二导电图案设置在半导体层上并位于该区域内。 棒状导电层位于第一电极线和第二电极线之间。 第一电极线和第二电极线分别与棒状导电层隔开第一距离和第二距离。 GOA结构具有连接到相应的第一导电图案和第一电极线的第一连接器,以及连接到第二导电图案和第二电极线的第二连接器。
    • 7. 发明申请
    • SHIFT REGISTER WITH LOW STRESS
    • 具有低应力的移位寄存器
    • US20080056430A1
    • 2008-03-06
    • US11682223
    • 2007-03-05
    • Lee-hsun ChangYu-wen LinYung-tse Cheng
    • Lee-hsun ChangYu-wen LinYung-tse Cheng
    • G11C19/00G09G3/36
    • G11C19/28G09G3/3677
    • A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.
    • 移位寄存器包括多个寄存器级。 每个寄存器级包括输出电路,第一开关电路和第二开关电路。 输出电路能够输出第一驱动信号。 当输出电路不输出第一驱动信号时,第一开关电路用于将输出电路下拉到低电压电平。 第二开关电路能够接收输入信号。 第一开关电路通过驻留在晶体管中的寄生电容器保持电荷,以便当输出电路不输出第一驱动信号时,保持第一开关电路处于导通状态。