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1. 发明申请

US20150178428A1 Analog Mixed Signal Model Equivalence Checking 有权
标题翻译：模拟混合信号模型等效性检查
公开(公告)号：US20150178428A1
公开(公告)日：2015-06-25
申请号：US14134488
申请日：2013-12-19
申请人： Himyanshu Anand , Magdy S. Abadir
发明人： Himyanshu Anand , Magdy S. Abadir
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.
摘要翻译：提供了一种混合混合信号等效性检查系统将混合信号参考模型和被验证的混合信号模型分为模拟部分和数字部分的方法。混合混合信号等效性检查系统模拟来自两个不同模型的模拟部分，以确定模拟等效性。这样，混合混合信号等效性检查系统响应于评估表示第一数字部分和第二数字部分的至少一部分的一个或多个差分函数来验证数字参考部分和数字部分模型之间的数字等效性。结果，混合混合信号等效性检查系统基于经验证的模拟等效性和验证的数字等价性来验证混合信号参考模型与正在验证的混合信号模型之间的等价性。

2. 发明授权

US07647573B2 Method and device for testing delay paths of an integrated circuit 有权
标题翻译：用于测试集成电路的延迟路径的方法和装置
公开(公告)号：US07647573B2
公开(公告)日：2010-01-12
申请号：US11442196
申请日：2006-05-26
申请人： Magdy S. Abadir , Jing Zeng , Benjamin N. Lee
发明人： Magdy S. Abadir , Jing Zeng , Benjamin N. Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/3016 , G01R31/318328
摘要： A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay measurements for the critical delay paths. The critical delay paths are ranked based on the actual delay measurements, and the results are correlated to the predicted ranking of critical delay paths to produce a confidence measurement that measures the likelihood that the actual critical delay paths of the design have been tested for a given production batch of devices.
摘要翻译：公开了一种测试集成电路设计的关键延迟路径的方法。该方法包括基于一组预测的延迟特性来预测和排列一组关键延迟路径。测试基于集成电路设计的集成电路，以确定关键延迟路径的一组实际延迟测量。关键延迟路径基于实际的延迟测量进行排序，并且结果与关键延迟路径的预测排序相关联，以产生置信度测量，该置信测量测量设计的实际临界延迟路径已经针对给定的测试生产批量的设备。

3. 发明申请

US20080071515A1 System and Method for Circuit Symbolic Timing Analysis of Circuit Designs 失效
标题翻译：电路设计电路符号定时分析系统与方法
公开(公告)号：US20080071515A1
公开(公告)日：2008-03-20
申请号：US11532268
申请日：2006-09-15
申请人： Jayanta Bhadra , Magdy S. Abadir , Ping Gao , Timothy David McDougall
发明人： Jayanta Bhadra , Magdy S. Abadir , Ping Gao , Timothy David McDougall
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.
摘要翻译：提供了一种方法，数据处理系统和计算机程序产品，用于执行基于时间的符号仿真。创建包括多个电路节点的电路的延迟感知表示。模拟数据感知表示。特别地，仿真器模拟从第一组电路节点到从多个电路节点选择的第二组电路节点的转换，基于执行第一组仿真事件进行仿真。响应于执行第一组模拟事件而产生第二组模拟事件。在仿真期间，为每个转换计算一个时间。在仿真期间构建事件调度图。事件调度图描述了转换和转换的时间。

4. 发明授权

US09594860B2 Analog mixed signal model equivalence checking 有权
标题翻译：模拟混合信号模型等价性检验
公开(公告)号：US09594860B2
公开(公告)日：2017-03-14
申请号：US14134488
申请日：2013-12-19
申请人： Himyanshu Anand , Magdy S. Abadir
发明人： Himyanshu Anand , Magdy S. Abadir
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.
摘要翻译：提供了一种混合混合信号等效性检查系统将混合信号参考模型和被验证的混合信号模型分为模拟部分和数字部分的方法。混合混合信号等效性检查系统模拟来自两个不同模型的模拟部分，以确定模拟等效性。这样，混合混合信号等效性检查系统响应于评估表示第一数字部分和第二数字部分的至少一部分的一个或多个差分函数来验证数字参考部分和数字部分模型之间的数字等效性。结果，混合混合信号等效性检查系统基于经验证的模拟等效性和验证的数字等价性来验证混合信号参考模型与正在验证的混合信号模型之间的等价性。

5. 发明申请

US20140132293A1 INTEGRATED CIRCUIT WITH DEGRADATION MONITORING 有权
标题翻译：集成电路与降解监测
公开(公告)号：US20140132293A1
公开(公告)日：2014-05-15
申请号：US13956126
申请日：2013-07-31
申请人： Magdy S. Abadir , Puneet Sharma
发明人： Magdy S. Abadir , Puneet Sharma
IPC分类号： G01R31/28 , H03K5/06
CPC分类号： G01R31/2882 , G01R31/31725 , H03K3/0375
摘要： An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
摘要翻译：一种包括劣化监测电路的集成电路。劣化监视电路包括具有可编程延迟元件的比较电路，该可编程延迟元件包括耦合到定时路径的数据节点的输入，并且具有输出以提供延迟可编程量的数据节点的数据信号的延迟信号。比较电路包括逻辑比较器，其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。监视电路包括采样电路，该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。监视电路包括保持电路，该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。

6. 发明授权

US06651227B2 Method for generating transition delay fault test patterns 有权
标题翻译：产生转移延迟故障测试模式的方法
公开(公告)号：US06651227B2
公开(公告)日：2003-11-18
申请号：US09986211
申请日：2001-10-22
申请人： Magdy S. Abadir , Juhong Zhu
发明人： Magdy S. Abadir , Juhong Zhu
IPC分类号： G06F1750
CPC分类号： G01R31/318328
摘要： A method of generating transition delay fault test patterns creates first and second circuit models of a received circuit model. The second circuit model is a replication of the first circuit model. Each latch of the first circuit model is identified. On a sequential basis until the entire circuit model is transformed, the data input of an identified latch in the first circuit model is disconnected and the data output of the corresponding latch in the second circuit model is disconnected. The driver of the data input of the latch in the first circuit model is connected to what was driven by the data output of the corresponding latch in the second circuit model to form a transformed circuit model. Stuck-at fault testing using conventional ATPG tools is performed on the transformed circuit model and the resulting test vectors are translated to generate transition fault test patterns for the original received circuit model.
摘要翻译：产生转移延迟故障测试模式的方法创建了接收电路模型的第一和第二电路模型。第二个电路模型是第一个电路模型的复制。识别第一电路模型的每个锁存器。直到整个电路模型被变换为止，在第一电路模型中识别的锁存器的数据输入被断开，并且第二电路模型中对应的锁存器的数据输出被断开。第一电路模型中锁存器的数据输入的驱动器连接到由第二电路模型中相应锁存器的数据输出驱动的驱动器，以形成变换电路模型。在变换电路模型上进行使用常规ATPG工具的故障测试，并将所得到的测试矢量转换为生成原始接收电路模型的转换故障测试模式。

7. 发明申请

US20110258588A1 INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE AND METHOD THEREFOR 有权
标题翻译：具有降低泄漏的集成电路装置及其方法
公开(公告)号：US20110258588A1
公开(公告)日：2011-10-20
申请号：US12762439
申请日：2010-04-19
申请人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
发明人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , G06F2217/78 , Y02P90/265
摘要： A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type.
摘要翻译：在计算机辅助设计工具中实现的方法包括优先地将与第一导电类型的晶体管相邻的填充区域放置在设备设计的多个标准单元实例中以减少多个标准单元实例的泄漏。与将第一导电类型相反的第二导电类型的晶体管相邻放置填充区域相比，优先放置填充区域包括优先地将填充区域放置成与第一导电类型的晶体管相邻。

8. 发明申请

US20100050139A1 DATA PROCESSING DEVICE DESIGN TOOL AND METHODS 有权
标题翻译：数据处理设备设计工具及方法
公开(公告)号：US20100050139A1
公开(公告)日：2010-02-25
申请号：US12196730
申请日：2008-08-22
申请人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
发明人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/16 , G06F2217/78
摘要： A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic.
摘要翻译：设计数据处理设备设计的方法包括确定热剖面信息以指示设计中设备实例的预测工作温度。器件实例与具有相对高的阈值电压特性的第一库单元相关联。基于热分布信息，并且基于与设备实例相关联的数据路径的定时信息，为设备实例确定成本函数值。基于成本函数值，与设备实例关联的库单元可以改变为具有较高阈值电压特性的单元。

9. 发明授权

US07650579B2 Model correspondence method and device 有权
标题翻译：模型对应方法和装置
公开(公告)号：US07650579B2
公开(公告)日：2010-01-19
申请号：US11441367
申请日：2006-05-25
申请人： Magdy S. Abadir , Himyanshu Anand , M. Alper Sen , Jayanta Bhadra
发明人： Magdy S. Abadir , Himyanshu Anand , M. Alper Sen , Jayanta Bhadra
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.
摘要翻译：公开了一种用于确定设计模型之间的存储元件和中间点对应的方法和装置。该方法包括开发电子设备的两个电路设计模型的图形表示。电路设计模型包括与电子设备的输入和输出节点相对应的输入和输出节点。电路设计模型还包括分别对应于电子设备的存储器元件和中间点的存储器和中间节点。中间点表示电子设备的存储元件之间的点，因此可以表示该设备的逻辑门或其他模块。存储元件和中间点可以统称为电路元件。图表中的节点表示设计模型中的输入，输出，存储元件或中间点。电路设计模型中的电路元件之间的对应关系是基于图形表示来确定的。

10. 发明授权

US09329229B2 Integrated circuit with degradation monitoring 有权
标题翻译：具有降级监控的集成电路
公开(公告)号：US09329229B2
公开(公告)日：2016-05-03
申请号：US13956126
申请日：2013-07-31
申请人： Magdy S Abadir , Puneet Sharma
发明人： Magdy S Abadir , Puneet Sharma
IPC分类号： H03M13/11 , G01R31/28 , G01R31/317 , H03K3/037
CPC分类号： G01R31/2882 , G01R31/31725 , H03K3/0375
摘要： An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
摘要翻译：一种包括劣化监测电路的集成电路。劣化监视电路包括具有可编程延迟元件的比较电路，该可编程延迟元件包括耦合到定时路径的数据节点的输入，并且具有输出以提供延迟可编程量的数据节点的数据信号的延迟信号。比较电路包括逻辑比较器，其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。监视电路包括采样电路，该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。监视电路包括保持电路，该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。

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