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1. 发明申请

US20110258588A1 INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE AND METHOD THEREFOR 有权
标题翻译：具有降低泄漏的集成电路装置及其方法
公开(公告)号：US20110258588A1
公开(公告)日：2011-10-20
申请号：US12762439
申请日：2010-04-19
申请人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
发明人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , G06F2217/78 , Y02P90/265
摘要： A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type.
摘要翻译：在计算机辅助设计工具中实现的方法包括优先地将与第一导电类型的晶体管相邻的填充区域放置在设备设计的多个标准单元实例中以减少多个标准单元实例的泄漏。与将第一导电类型相反的第二导电类型的晶体管相邻放置填充区域相比，优先放置填充区域包括优先地将填充区域放置成与第一导电类型的晶体管相邻。

2. 发明授权

US08898614B2 Integrated circuit device with reduced leakage and method therefor 有权
标题翻译：具有减少泄漏的集成电路装置及其方法
公开(公告)号：US08898614B2
公开(公告)日：2014-11-25
申请号：US12762439
申请日：2010-04-19
申请人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
发明人： Puneet Sharma , Magdy S. Abadir , Scott P. Warrick
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5072 , G06F2217/12 , G06F2217/78 , Y02P90/265
摘要： A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.
摘要翻译：一种方法包括为设备设计的多个标准单元实例优先地将与特定导电类型的晶体管（例如p沟道晶体管）相邻的填充区域放置。该方法还包括在评估第二导电类型的任何晶体管之前评估第一导电类型的所有晶体管。第二导电类型与第一导电类型相反。对于正在评估的每个晶体管，确定一个标准是否为我。如果满足标准，则将填充区域放置在与晶体管相邻的场隔离区域内。

3. 发明申请

US20140132293A1 INTEGRATED CIRCUIT WITH DEGRADATION MONITORING 有权
标题翻译：集成电路与降解监测
公开(公告)号：US20140132293A1
公开(公告)日：2014-05-15
申请号：US13956126
申请日：2013-07-31
申请人： Magdy S. Abadir , Puneet Sharma
发明人： Magdy S. Abadir , Puneet Sharma
IPC分类号： G01R31/28 , H03K5/06
CPC分类号： G01R31/2882 , G01R31/31725 , H03K3/0375
摘要： An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
摘要翻译：一种包括劣化监测电路的集成电路。劣化监视电路包括具有可编程延迟元件的比较电路，该可编程延迟元件包括耦合到定时路径的数据节点的输入，并且具有输出以提供延迟可编程量的数据节点的数据信号的延迟信号。比较电路包括逻辑比较器，其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。监视电路包括采样电路，该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。监视电路包括保持电路，该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。

4. 发明授权

US09329229B2 Integrated circuit with degradation monitoring 有权
标题翻译：具有降级监控的集成电路
公开(公告)号：US09329229B2
公开(公告)日：2016-05-03
申请号：US13956126
申请日：2013-07-31
申请人： Magdy S Abadir , Puneet Sharma
发明人： Magdy S Abadir , Puneet Sharma
IPC分类号： H03M13/11 , G01R31/28 , G01R31/317 , H03K3/037
CPC分类号： G01R31/2882 , G01R31/31725 , H03K3/0375
摘要： An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
摘要翻译：一种包括劣化监测电路的集成电路。劣化监视电路包括具有可编程延迟元件的比较电路，该可编程延迟元件包括耦合到定时路径的数据节点的输入，并且具有输出以提供延迟可编程量的数据节点的数据信号的延迟信号。比较电路包括逻辑比较器，其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。监视电路包括采样电路，该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。监视电路包括保持电路，该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。

5. 发明申请

US20100050139A1 DATA PROCESSING DEVICE DESIGN TOOL AND METHODS 有权
标题翻译：数据处理设备设计工具及方法
公开(公告)号：US20100050139A1
公开(公告)日：2010-02-25
申请号：US12196730
申请日：2008-08-22
申请人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
发明人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/16 , G06F2217/78
摘要： A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic.
摘要翻译：设计数据处理设备设计的方法包括确定热剖面信息以指示设计中设备实例的预测工作温度。器件实例与具有相对高的阈值电压特性的第一库单元相关联。基于热分布信息，并且基于与设备实例相关联的数据路径的定时信息，为设备实例确定成本函数值。基于成本函数值，与设备实例关联的库单元可以改变为具有较高阈值电压特性的单元。

6. 发明授权

US08127258B2 Data processing device design tool and methods 有权
标题翻译：数据处理设备的设计工具和方法
公开(公告)号：US08127258B2
公开(公告)日：2012-02-28
申请号：US12196730
申请日：2008-08-22
申请人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
发明人： Magdy S. Abadir , Aseem Gupta , Kamal S. Khouri , Puneet Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/16 , G06F2217/78
摘要： A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic.
摘要翻译：设计数据处理设备设计的方法包括确定热剖面信息以指示设计中设备实例的预测工作温度。器件实例与具有相对高的阈值电压特性的第一库单元相关联。基于热分布信息，并且基于与设备实例相关联的数据路径的定时信息，为设备实例确定成本函数值。基于成本函数值，与设备实例关联的库单元可以改变为具有较高阈值电压特性的单元。

7. 发明授权

US10162932B2 Method and system for multi-scale anatomical and functional modeling of coronary circulation 有权
公开(公告)号：US10162932B2
公开(公告)日：2018-12-25
申请号：US13672781
申请日：2012-11-09
申请人： Puneet Sharma , Lucian Mihai Itu , Bogdan Georgescu , Viorel Mihalef , Ali Kamen , Dorin Comaniciu
发明人： Puneet Sharma , Lucian Mihai Itu , Bogdan Georgescu , Viorel Mihalef , Ali Kamen , Dorin Comaniciu
IPC分类号： G06F19/12 , G16H50/50 , G06F19/00 , G16H50/30
摘要： A method and system for multi-scale anatomical and functional modeling of coronary circulation is disclosed. A patient-specific anatomical model of coronary arteries and the heart is generated from medical image data of a patient. A multi-scale functional model of coronary circulation is generated based on the patient-specific anatomical model. Blood flow is simulated in at least one stenosis region of at least one coronary artery using the multi-scale function model of coronary circulation. Hemodynamic quantities, such as fractional flow reserve (FFR), are computed to determine a functional assessment of the stenosis, and virtual intervention simulations are performed using the multi-scale function model of coronary circulation for decision support and intervention planning.

8. 发明申请

US20150305706A1 ESTIMATION OF A MECHANICAL PROPERTY OF ANATOMY FROM MEDICAL SCAN DATA 有权
标题翻译：从医学扫描数据估计解剖学的机械性质
公开(公告)号：US20150305706A1
公开(公告)日：2015-10-29
申请号：US14259801
申请日：2014-04-23
申请人： Jingjing Kanik , Puneet Sharma , Tommaso Mansi , Razvan Ionasec , Ali Kamen , Dorin Comaniciu , James S. Duncan
发明人： Jingjing Kanik , Puneet Sharma , Tommaso Mansi , Razvan Ionasec , Ali Kamen , Dorin Comaniciu , James S. Duncan
IPC分类号： A61B8/08
CPC分类号： A61B8/0883 , A61B8/5223 , A61B8/5276
摘要： A mechanical property of anatomy is estimated from a patient in vivo, such as estimating a patient-specific material property of a valve. A morphological model is used to determine anatomy dynamics. A biomechanical model, using the anatomy dynamics, predicts the dynamics, based, at least in part, on one or more material properties. Using an inverse solution based on comparison of dynamics predicted by the biomechanical model and the dynamics determined from the morphological model, values for the material properties are determined.
摘要翻译：从患者身体估计解剖学的机械性质，例如估计瓣膜的患者特异性材料性质。使用形态学模型来确定解剖动力学。使用解剖动力学的生物力学模型预测动力学，至少部分地基于一种或多种材料性质。使用基于生物力学模型预测的动力学与从形态学模型确定的动力学的比较的逆解决方案，确定材料性质的值。

9. 发明授权

US08965084B2 Blood flow computation in vessels with implanted devices 有权
标题翻译：带有植入装置的血管中的血流计算
公开(公告)号：US08965084B2
公开(公告)日：2015-02-24
申请号：US13744857
申请日：2013-01-18
申请人： Viorel Mihalef , Puneet Sharma , Thomas Redel , Ali Kamen
发明人： Viorel Mihalef , Puneet Sharma , Thomas Redel , Ali Kamen
IPC分类号： G06K9/00 , G06K9/36 , G06F19/00 , G06T19/00 , A61B6/03 , A61B6/00
CPC分类号： G16H50/50 , A61B6/032 , A61B6/486 , A61B6/504 , A61B6/5217 , G06T19/00 , G06T2210/41
摘要： A method for modeling blood flow through a flow diverter includes receiving a medical image containing blood vessels. Vessel geometry is extracted from the received medical image. Inlets and outlets are tagged within the extracted vessel geometry. A desired flow diverter is selected. A model of the selected flow diverter is generated within the imaged blood vessel, the model representing the flow diverter as a tube having a porous surface characterized by a viscous resistance and an inertial resistance. A course of blood flow though the flow diverter is predicted based on the generated model, the extracted vessel geometry, and the tagged inlets and outlets.
摘要翻译：通过流转向器对血液流动进行建模的方法包括接收包含血管的医学图像。从接收到的医学图像中提取血管几何。进口和出口在提取的容器几何中被标记。选择所需的分流器。所选流量分流器的模型在成像的血管内产生，该模型表示流量分流器为具有以粘性阻力和惯性阻力为特征的多孔表面的管。基于生成的模型，提取的血管几何形状和标记的入口和出口预测通过流量分流器的血液流动过程。

10. 发明申请

US20140132315A1 INTEGRATED CIRCUIT WITH DEGRADATION MONITORING 有权
标题翻译：集成电路与降解监测
公开(公告)号：US20140132315A1
公开(公告)日：2014-05-15
申请号：US13677800
申请日：2012-11-15
申请人： Puneet Sharma , Matthew A. Thompson , Willard E. Conley
发明人： Puneet Sharma , Matthew A. Thompson , Willard E. Conley
IPC分类号： H03L7/00
CPC分类号： G01R31/3016 , G01R31/2884
摘要： An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.
摘要翻译：一种包括劣化监测电路的集成电路。劣化监视电路包括具有延迟元件的比较电路，该延迟元件包括耦合到定时路径的数据节点的输入，并具有输出以提供数据节点的数据信号的延迟信号。比较电路包括逻辑比较器，其提供数据节点的数据信号和延迟元件的输出之间的逻辑比较。监视电路包括采样电路，该采样电路提供对于时钟信号线的时钟信号采样的逻辑比较器的输出的采样信号。监视电路包括保持电路，该保持电路提供指示在时钟信号线的时钟信号的边沿转换的预定时间内数据节点的数据信号的信号。

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